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RZ/T1 Datenblatt(PDF) 133 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 133 Page - Renesas Technology Corp |
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133 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 133 of 139 Jun. 30, 2025 RZ/T1 Group 1.30 Apr. 25, 2017 1. Overview 49 Table 1.8 List of Pin and Pin Functions (176-Pin HLQFP) (6/6): The communication function of pin 171, modified 2. Electrical Characteristics 107 Figure 2.60 SPIBSC Transmit/Receive Timing (CPHAT = 0, CPHAR = 1): Modified 1.40 Nov. 15, 2017 All Cortex-R4F changed to Cortex-R4 Features 1 ■ Encoder interfaces, changed ■ Various communications interfaces: Features of Ethernet changed 1. Overview 2 1.1 Outline of Specifications: "Cortex®-R4F processor" changed to "Cortex®-R4 processor with FPU" 8 Table 1.1 Outline of Specifications (7 / 7): Description of the encoder interfaces changed 16 Table 1.4 Pin Functions (4 / 7): CTS0# to CTS4#: I/O and functional description changed; RTS0# to RTS4#: Functional description changed 19 Table 1.4 Pin Functions (7 / 7): ENCIF07 to ENCIF12 changed to ENCIF00 to ENCIF12 22 Table 1.5 Pin Assignments (320-Pin FBGA) (1 / 8): ENCIF12 added to B19; ENCIF11 added to B20 23 Table 1.5 Pin Assignments (320-Pin FBGA) (2 / 8): ENCIF10 added to C19; ENCIF09 added to D19; ENCIF08 added to E19 24 Table 1.5 Pin Assignments (320-Pin FBGA) (3 / 8): ENCIF11 added to H19; ENCIF12 added to H20 25 Table 1.5 Pin Assignments (320-Pin FBGA) (4 / 8): ENCIF10 added to J19 26 Table 1.5 Pin Assignments (320-Pin FBGA) (5 / 8): ENCIF09 added to N20; ENCIF08 added to P20 27 Table 1.5 Pin Assignments (320-Pin FBGA) (6 / 8): ENCIF09 added to U3 28 Table 1.5 Pin Assignments (320-Pin FBGA) (7 / 8): ENCIF10 added to W3; ENCIF11 added to W4; ENCIF08 added to W10; ENCIF12 added to Y4 35 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (2 / 10): ENCIF12 added to B19 under "Others"; ENCIF11 added to B20 under "Others" 36 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (3 / 10): ENCIF10 added to C19 under "Others"; ENCIF09 added to D19 under "Others"; ENCIF08 added to E19 under "Others" 38 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (5 / 10); ENCIF11 added to H19 under "Others"; ENCIF12 added to H20 under "Others"; ENCIF10 added to J19 under "Others" 40 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (7 / 10): ENCIF09 added to N20 under "Others"; ENCIF08 added to P20 under "Others" 41 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (8 / 10): ENCIF09 added to U3 under "Others" 42 Table 1.7 List of Pin and Pin Functions (320-Pin FBGA) (9 / 10): ENCIF10 added to W3 under "Others"; ENCIF11 added to W4 under "Others"; ENCIF08 added to W10 under "Others; ENCIF12 added to Y4 2. Electrical Characteristics 65, 66 Table 2.17 Bus Timing: "CKIO = 75MHz" changed to "CKIO = 1/tCKcyc; "tcyc" changed to "tCKcyc"; entries for "Address delay time 1", "CS# delay time 1", "Read/write delay time 1", "Read data setup time 1 to 3" and "WAIT# setup time" changed; Notes 1, 3, and 4 changed 102 Table 2.27 RSPIa Timing: Note 2 changed (SSLND → SPCKD): Note 3 added 111 Figure 2.64 RIICa Bus Interface Input/Output Timing: SDA0 to SDA3 and SCL0 to SCL3 deleted Rev. Date Description Page Summary |
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