SPRUG18 datasheet(117/214 Pages) TI

117 / 214 page

MainPLL

AIFSERDES0

x12.5,10,4

AIFSERDES1

x12.5,10,4

Main.PLL Controller

ToL2andL2PDCTL

C64x+Megamodule

Core0

C64x+Megamodule

Core1

C64x+Megamodule

Core2

ToTrace

/20

Reserved

CHIP_CLK3

CHIP_CLK6

McBSP_CLKS

EMIF_PTV

Toswitchfabric

peripherals,

accelerators

SYS_CLK_(PIN)

ALT_CORE_CLK_(PIN)

CORE_CLK_SEL

DD118

/20

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.8

PLL1 and PLL1 Controller

This section provides a description of the PLL1 controller registers. For details on the operation of the PLL

controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)

Controller User's Guide (literature number SPRUG09).

Note: The PLL1 controller registers can only be accessed using the CPU or the emulator.

Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked

Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.

Only those registers documented in this section are supported. Furthermore, only the bits within the

registers described here are supported. You should not write to any reserved memory location or change

the value of reserved bits.

The Main and DDR PLLs are controlled by standard PLL Controller peripherals. The PLL Controllers

manage the clock ratios, alignment, and gating for the system clocks to the chip. Figure 7-10 includes a

block diagram of the PLL Controller, and the two subsequent sections define the clocks and PLL

Controller parameters for each of the two standard PLLs.

The PLL controller logic is responsible for controlling all modes of the PLL through software, in terms

multiply factor within the PLL and post-division for each of the chip-level clocks from the PLL output. The

PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL

controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Figure 7-10. PLL Controller Diagram

Peripheral Information and Electrical Specifications

117

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