SSM4567ACBZ-R7 datasheet(29/52 Pages) AD

29 / 52 page

Data Sheet

SSM4567

Rev. 0| Page 29 of 52

SOFTWARE CONTROL MODE, PDM INTERFACE

Figure 55. Typical Application Circuit, PDM, Software Control Mode

Description

In this application circuit, the SSM4567 is controlled by an external master on the I2C interface. The I2C address is configured using the

LR_SEL/ADDR pin. The serial data interface is initially set to PCM mode, as configured by the SEL pin, but must be changed to PDM

mode using register writes when configuring the device via I2C.

Pin Configuration

Table 22. Pin Configuration for I2S Software Control Applications, Software Control Mode, PDM Interface

Hardware Pin

Connection

LR_SEL/ADDR

Connect to AGND for I2C Address 0x34; IOVDD for I2C Address 0x35; leave open for I2C Address 0x36.

SEL

Connect to IOVDD for I2C control mode.

SNS_PDM_CLK/FSYNC

Connect to an external PDM clock signal for sense data.

DAC_PDM_CLK/BCLK

Connect to an external PDM clock signal for audio data.

SNS_PDM_DAT/SNS_SDATAO

Sends current, voltage, and battery sense data in PDM format to an external IC.

DAC_PDM_DAT/DAC_SDATAI

Receives a serial audio data signal in PDM format from an external IC.

SCL

Connect to the clock signal of an external I2C master IC.

SDA

Connect to data signal of an external I2C master IC.

I2S/TDM/

PDM

INTERFACE

H-BRIDGE

(5V)

SENSE

Σ-Δ

CLASS-D

MOD

FILTERING

MODULATION

BOOST (5V)

OUTP

OUTN

22µF

10µF

1µF

2.2µH

VBAT

AGND

IOVDD

SSM4567

LR_SEL/

ADDR

SEL

BSTSW

IOVDD

BSTSW

VBST

PGND

SCL

SDA

DAC

ADC

VBAT

0.1µF

IOVDD

1µF

DAC_PDM_CLK/

BCLK

SNS_PDM_CLK/

FSYNC

SNS_PDM_DAT/

SNS_SDATAO

DAC_PDM_DAT/

DAC_SDATAI

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