SSM4567ACBZ-R7 datasheet(17/52 Pages) AD

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Data Sheet

SSM4567

Rev. 0| Page 17 of 52

PDM CHANNEL SELECTION

The SSM4567 includes a left/right input select pin,

LR_SEL/ADDR (see Table 24) that determines which of the

time-multiplexed input streams is routed to the amplifier when

using PDM pattern control mode. To select the left input

channel, connect LR_SEL/ADDR pin to AGND. To select right

channel data, connect LR_SEL/ADDR pin to IOVDD. At any

point during amplifier operation, the logic level applied to

LR_SEL/ADDR pin can be changed and the output switches

between input streams without audible artifacts. Aside from

logic level selection from the user, no muting, watermarking

pattern, or synchronizing is necessary to achieve a click/pop

free LR_SEL/ADDR transition.

Table 8. LR_SEL/ADDR Function Descriptions

Device Setting

LR_SEL/ADDR Pin Configuration

Right Channel Select

IOVDD

Left Channel Select

GND

PCM MODE PIN SETUP AND CONTROL

When the SEL pin is tied to IOVDD, the SSM4567 is set for

PCM mode operation. In this mode, the SSM4567 supports

standalone operation, I2C control, or can be controlled using

commands sent over the input serial audio/TDM interface.

When the LR_SEL/ADDR pin is pulled up via a 47 kΩ resistor,

the IC operates in standalone mode with most registers set to

their default states.

The state of the several pins can change the functionality of

other pins. The LR_SEL/ADDR pin determines the I2C device

address. In standalone and TDM control modes, the SCL and SDA

pins are used to determine the TDM slot used. See Table 10 for

details.

PCM DIGITAL AUDIO SERIAL INTERFACE

The SSM4567 includes a standard serial audio interface that is

slave only. The interface is capable of receiving and transmitting

I2S, left justified, PCM, or TDM formatted data.

There is an input interface for sending audio to the amplifier

and an output interface for the sense data. These interfaces

share the same FSYNC and BCLK signals.

A BCLK signal must be provided to the SSM4567 for correct

operation. The BCLK signal must have a minimum frequency

of 2 MHz. The BCLK signal is used for internal clocking of the

device. The BCLK rate is automatically detected, but the

sampling frequency must be known to the device. The BCLK

rates at 32 kHz to 48 kHz that are supported are 50, 64, 100,

128, 192, 200, 256, 384, 400, and 512 times the sample rate.

The serial interfaces have three main operating modes. Stereo

mode, typically I2S or left justified, is used when there is a single

chip on the interface bus. TDM mode is more flexible and offers

the ability to have multiple chips on the bus. The third operating

mode is multichip I2S mode, which uses standard I2S formatting

but allows multiple chips to use the bus.

It is also possible to use the serial interfaces for bidirectional

control information. When this is done, the internal control reg-

isters are accessed via the serial audio interface and not from I2C.

These mode selections can be set via the I2C interface with the

SAI_MODE and MC_I2S bits. Alternatively, in standalone

mode or when AUTO_SAI is set to 1, the interface can auto-

configure based on how the signals are connected to the clock

pins and the FSYNC type (pulse or 50% duty cycle).

When in standalone or automatic configuration modes, an I2S

interface format can be selected by swapping the pin

connections for the BCLK and FSYNC signals (with the I2S

LRCLK signal connected to the DAC/PDM_CLK/BCLK pin

and BCLK signal connected to the SNS_PDM_CLK/FSYNC

pin). When the BCLK and FSYNC signals are connected to

their respective pins, and the FYSNC signal is a single BCLK

cycle pulse, TDM mode is selected. When the BCLK and FSYNC

signals are connected to their respective pins, and the FYSNC

signal is a 50% duty cycle signal, multichip I2S mode is selected.

On the SNS_PDM_DAT/SNS_SDATAO pin, unused cycles can

either be driven or set to high-Z. This is determined by the

SAI_DRV control bit. If multiple chips are used on the serial

interface bus, then SAI_DRV must be set to 0 so that unused

cycles are not driven.

SERIAL DATA PLACEMENT

The SSM4567 is flexible in where within a frame it places

output data and where it looks for input data. There are four

control bits for when input data is expected (Px_DAC) and and

six control bits for when output data is driven (Px_SNS).

A single data frame is broken up into individual fields, referred

to as placements. Each placement can be 8 bits, 16 bits, or 24 bits in

length. A single frame on the TDM or I2S data stream can

contain several data placements of varying length.

When the serial port is operating in TDM mode, placements

start directly after the FSYNC pulse. The first placement is

referred to as P1, the second placement is referred to as P2, and

so on, increasing sequentially. These placements appear in

sequential order on the serial data signal. Up to four placements

can be on the input stream and up to six placements can be on

the output stream. Figure 37 shows a basic timing diagram of

the placements in TDM mode.

When the serial port is operating in I2S mode, placements start

directly after the FSYNC falling clock edge, signalling the

beginning of a new frame. The first placement is referred to as

P1, the second placement is referred to as P2, and so on, increasing

sequentially. The odd-numbered placements (P1, P3, and P5)

appear sequentially in the left channel, when the FSYNC signal

is low (assuming FSYNC_MODE = 0), and the even-numbered

placements (P2, P4, and P6) appear sequentially in the right

channel, when the FSYNC signal is high (assuming that

FSYNC_MODE = 0. Up to four placements can be on the input

stream and up to six placements can be on the output stream.

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