SSM4567ACBZ-R7 datasheet(15/52 Pages) AD

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Data Sheet

SSM4567

Rev. 0| Page 15 of 52

THEORY OF OPERATION

MODES OF OPERATION

The SSM4567 has several modes of control and audio I/O

operation. Audio and sense data can be sent to and from the

SSM4567 in 1-bit PDM format by tying the SEL pin to AGND

or multibit PCM format by tying the SEL pin to IOVDD. With

PCM data, the serial audio interface can be configured for I2S,

left justified, or TDM formatting. The SSM4567 can be

controlled using I2C, PDM pattern control, TDM control, or

standalone operation. See Table 10 for more details.

CLOCKING

The SSM4567 requires a clock present at the DAC_PDM_CLK/

BCLK input pin to operate. This clock must be fully synchronous

with the incoming digital data. The clock frequencies must fall

in the range of 2.048 MHz to 24.576 MHz for PCM mode, or

2.048 MHz to 6.144 MHz for PDM mode.

In standalone I2S mode, the required clock must be present on

the SNS_PDM_CLK/FSYNC pin.

POWER SUPPLIES

The SSM4567 requires two power supplies: VBAT and IOVDD.

VBAT

VBAT supplies power to the boost converter and its associated

drive, control, and protection circuitry. VBAT can operate from

2.5 V to 5.2 V and must be present to obtain audio output.

IOVDD

IOVDD provides power to the digital logic circuitry and the I/O

drive circuitry. IOVDD can operate from 1.62 V to 1.98 V and

must be present to obtain audio output.

Power Sequencing

On device power-up, VBAT must be applied to the device first.

The timing of the IOVDD following VBAT is not important. See

the Power-On Reset/Voltage Supervisor section for more details.

POWER CONTROL

The SSM4567 can be powered down by several methods. If

using I2C or TDM control, a software power-down control

SPWDN fully powers down the device. PDM pattern control

has a standby pattern that powers down all blocks except the

PDM interface.

For lowest power shutdown, the SSM4567 also contains a clock

loss detection circuit that looks at the DAC_PDM_CLK/BCLK

input clock. When DAC_PDM_CLK/BCLK is absent, the device

automatically powers down all internal circuitry to its lowest

power state. When DAC_PDM_CLK/BCLK returns, the device

automatically powers up following its usual power sequence.

There is an optional automatic power-down feature in which

the device enters a lower power state after 2048 consecutive

zero input samples have been received when in PCM operation.

Only the I2C and digital audio input blocks remain active.

The output current, output voltage, and VBAT sensing can be

turned off independently via the ISNS_PWDN, VSNS_PWDN,

and BSNS_PWDN control bits. This can save power if the

amplifier operation is needed but not the output sensing.

The amplifier and boost converter can be powered down

independently via the AMP_PWDN and BOOST_PWDN

control bits. When the boost is powered down and the amplifier

is still active, the amplifier runs directly from the VBAT supply.

This same VBAT only operation can be entered with the boost

still active with the VBAT_ONLY bit. The amplifier can be

powered down with the boost still enabled so the boost output

can be used for other functions.

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM4567 includes an internal power-on reset and voltage

supervisor circuit. This circuit provides an internal reset to all

circuitry whenever VBAT or IOVDD is substantially below the

nominal operating threshold. This simplifies supply sequencing

during initial power-on.

The circuit also monitors the power supplies to the IC. If the

supply voltages fall below the nominal operating threshold, this

circuit stops the output and issues a reset. This ensures that no

damage occurs due to low voltage operation and that no pops

can occur under nearly any power removal condition.

PDM MODE SETUP AND CONTROL

The SSM4567 can operate using 1-bit PDM data for both its

input and for the sense outputs. In PDM mode, control can be

done either by PDM control patterns or with I2C. If the SEL pin

is tied to AGND, the SSM4567 starts up and operate in PDM

pattern control mode.

The SSM4567 can also operate in PDM via I2C control mode. A

regular I2C operating address can be set on the LR_SEL/ADDR pin.

Then, using I2C, the device can be set into PDM mode by

writing a 1 to the PDM_MODE control bit. The PDM_LR_SEL

bit selects which input channel is used.

In PDM operating mode mode, the 1-bit PDM input to the

DAC is received on the DAC_PDM_DAT/DAC_SDATAI pin.

The DAC_PDM_CLK/BCLK pin provides the system clock and

is used for clocking in the input data. Output voltage and current

sense are output on the SNS_PDM_DAT/SNS_SDATAO pin. The

output can be sent at a different rate from the input, and the

SNS_PDM_CLK/FSYNC pin determines the sense output rate.

Alternatively, the output rate can be sent at the same rate as the

input and only one clock pin, DAC_PDM_CLK/BCLK, is

needed to operate the device. To use only one clock, set the

SHARED_CLOCK register to 1.

Full-scale voltage for both the input and output is mapped to

−6 dBFS on the PDM stream.

The PDM data input is registered directly on each clock edge.

The data transition on the PDM data output is delayed relative

to the clock edge.

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