SSM4567ACBZ-R7 datasheet(24/52 Pages) AD

24 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 24 of 52

TDM CONTROL INTERFACE

The SSM4567 supports control data sent over the serial audio

interface (SAI). This allows flexible control of the device

without requiring an I2C control port connection. Only TDM

operation with 64 BCLKs per chip is supported in this mode

(see Figure 50). It is not possible to modify any of the SAI

control registers in this mode. The placement for DAC inputs,

Px_DAC, also cannot be modified. The placements for sense

outputs, Px_SNS, can be modified. An 8-bit control data output

can be placed on the SNS_PDM_DAT/SNS_SDATAO line via

the placement register. This allows reading of control data over

the SAI. It is not necessary to use this in SAI control mode.

Figure 51. SDATAI Data Placement for SAI Control, TDM with 64-Bit Slot

Two bytes, the control header and control data, must be placed

in the DAC input stream and one byte, control data, is placed

on the output sense stream.

The three LSBs of the control header byte are used to initiate

control sequences. They are the start bit indicating the start of a

control sequence when set to one, the stop bit indicating the stop of

a control sequence when set to one, and the read/write bit, which

indicates a read or write sequence when the start bit is also set.

Figure 52. SAI Control Header Byte Format

The control data sequencing is the same as I2C control, except a

device address is not required. The first control data byte sent

after the start is the 8-bit subaddress; the subsequent control

data bytes are data.

Table 17. SAI Control Write Sequence

Frame

Control

Header

Control

DAC_DATAI

Control

SNS_DATAO

0x04

Subaddress

0x00

Data 1

0x00

Data 2

0x00

Data 3

0x00

0x02

Don’t care

0x00

Table 18. SAI Control Read Sequence

Frame

Control

Header

Control

DAC_DATAI

Control

SNS_DATAO

0x05

Subaddress

0x00

Don’t care

Data 1

0x00

Don’t care

Data 2

0x00

Don’t care

Data 3

0x02

Don’t care

0x00

STANDALONE MODE CONTROL

The SSM4567 can be operated without any control interface in

standalone mode. This mode is set by pulling up the

LR_SEL/ADDR pin to IOVDD with a 47 kΩ resistor. When

operating in standalone mode, all control settings are set to

their default state except for those listed in Table 19.

Table 19. Non Default Register Settings in Standalone Mode

Bit Name

SA_MODE Setting

Function

SPWDN

Normal operation

AUTO_SAI

Auto detection of serial

audio interface format

LIM_EN

Disable limiter

SDATA_FMT

Normal I2S

TDM_BCLKS

64 BCLKs per chip in

TDM

PDM_MODE

Disable PDM mode

In standalone mode with the interface set to TDM mode, the

SDA pin and the SCL pin are used to select the TDM/channel

slot. If in I2S mode, the SCL pin can be used to power down

boost, and the SDA pin can be used to shut down the whole

device (see Table 10).

EMI NOISE

The SSM4567 uses a proprietary modulation and spread-

spectrum technology to minimize EMI emissions from the

device. The SSM4567 can pass FCC Class B emissions testing

with unshielded 20-inch cable using ferrite bead-based filtering.

For applications that have difficulty passing FCC Class B

emission tests, the SSM4567 includes an edge rate control bit,

significantly reduces the radiated emissions at the Class-D

outputs, particularly above 100 MHz. Note that reducing the

supply voltage also greatly reduces radiated emissions.

OUTPUT MODULATION DESCRIPTION

The SSM4567 uses five-level, Σ-Δ output modulation. Each

output can swing from PGND to VBAT or PGND to VBST at

any time and vice versa. Ideally, when no input signal is present,

the output differential voltage is 0 V, because there is no need to

generate a pulse. In a real-world situations, there are always

noise sources present.

Due to this constant presence of noise, a differential pulse is

generated, when required, in response to this stimulus. A small

amount of current flows into the inductive load when the

differential pulse is generated.

Most of the time, however, output differential voltage is 0 V, due

to the Analog Devices, Inc., five-level, Σ-Δ output modulation.

This feature ensures that the current flowing through the

inductive load is small.

CONTROL HEADER 8-BIT

CONTROL DATA 8-BIT

BLANK

DAC 24-BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

START

STOP

R/W

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