SSM4567ACBZ-R7 datasheet(21/52 Pages) AD

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Data Sheet

SSM4567

Rev. 0| Page 21 of 52

OUTPUT CURRENT SENSING

The SSM4567 uses an on-chip sense resistor to determine the

output current flowing to the load. The voltage across this sense

resistor is proportional to the load current and sent to an ADC

running nominally at 128 × fs. In PCM mode, the output of this

ADC is downsampled using digital filtering. This downsampled

signal at an 8 kHz to 192 kHz sample rate is output on the

digital audio interface. The data is 16 bits and in signed fraction

format. For both current and voltage sensing a sample rate equal

to the DAC input is the default setting. A lower sample rate of ½,

¼, or ⅛ the DAC sample rate can be used. This can be set using

the SNS_FS bits, Register 0x01[5:4].

In PDM mode the sense ADC runs at the PDM clock rate.

OUTPUT VOLTAGE SENSING

The output voltage level is monitored and sent to an ADC

running nominally at 128 × fs. The output of this ADC is then

downsampled using digital filtering. This downsampled signal

at 8 kHz to 192 kHz sample rate is output on the digital audio

interface. The data is 16 bits and in signed fraction format. For

both current and voltage sensing, a sample rate equal to the

DAC input is the default setting. A lower sample rate of ½, ¼, or

⅛ the DAC sample rate can be used. This can be set using the

SNS_FS bits, Register 0x01[5:4].

In PDM mode, the sense ADC runs at the PDM clock rate.

VBAT SENSING

The SSM4567 contains an 8-bit ADC that measures the voltage

of the VBAT supply in real time. The output of the ADC is in 8-bit

unsigned format and is presented on the eight MSBs of the 16

bits in Slot 3 on the TDM bus. The remaining eight LSBs are

driven low (see Figure 39).

LIMITER AND BATTERY TRACKING THRESHOLD

CONTROL

The SSM4567 contains an output limiter that can limit the peak

output voltage of the amplifier. The threshold at which the

output is limited is determined by the LIM_THRES register

setting, Register 0x0E[3:0]. The audio signal is not affected by

the limiter function unless the peak audio output voltage

exceeds the limiter threshold level.

The LIM_THRES can be set above the maximum output voltage

of the amplifier. In this case, the limiter allows maximum peak

output, but limits the amount of clipping that can occur. The

rate of gain reduction or attack rate and gain increase or release

rate is determined by the LIM_ATR bits (Register 0x0E[5:4]) and

LIM_RRT bit (Register 0x0E[7:6]), respectively.

The SSM4567 can monitor the VBAT supply and automatically

adjust the limiter threshold when the VBAT supply is below a

selected point when LIM_EN = 01. When using the limiter, it

can be selected whether the threshold is fixed or moves with the

battery voltage via the VBAT_TRACK bit (Register 0x0D[2]). This

function can prevent early shutdown under end-of-charge

battery conditions. The VBAT supply voltage at which the limiter

level begins to decrease the output level is determined by the

VBAT_INF bits (Register 0x0D[5:3]). The rate at which the

threshold is lowered relative to the amount VBAT has lowered

below the VBAT_INF point is determined by the slope bits

(Register 0x0D[7:6]).

The limiter can also be set such that it engage only when the

battery voltage is lower than VBAT_INF by setting LIM_EN = 11.

When VBAT is above VBAT_INF, no limiting takes place. In this

case, there is hysteresis on VBAT_INF for the limiter disengaging.

If LIM_EN = 10, when VBAT falls below the VBAT_INF value,

the amplifier automatically mutes. In this case, there is

hysteresis on VBAT_INF when the mute is disengaged.

Figure 41. Battery Tracking Limiter Threshold Control

Figure 42. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0b1)

Figure 43. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0)

VBAT

VBAT_INF

LIM_THRES

SLOPE

VBAT

LIM_EN = 11

VBAT_TRACK = 1

NO LIMITING

VBAT

LIM_EN = 11

VBAT_TRACK = 0

NO LIMITING

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