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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SSM4567ACBZ-R7 Datenblatt(PDF) 1 Page - Analog Devices |
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SSM4567ACBZ-R7 Datenblatt(HTML) 1 Page - Analog Devices |
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1 / 52 page  Digital 2.5 W, 5.1 V, Boost Class-D Audio Amplifier with Output Sensing Data Sheet SSM4567 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Filterless Class-D amplifier with spread-spectrum Σ-Δ modulation with integrated boost regulator (5.1 V) Digitized output of output voltage, output current, and VBAT supply voltage Integrated boost regulator Multiple serial data formats PDM input/output TDM slave with support for up to 8 chips on a single bus I2S or left justified slave Multichip I2S with support for up to 4 chips on one I2S bus 8 kHz to 192 kHz PCM sample rates 2.048 to 6.14 MHz PDM input sample rates Configurable via I2C control, TDM control, or PDM patterns Standalone control modes 2.5 W into 4 Ω load and 1.42 W into 8 Ω load at 3.6 V supply with <1% total harmonic distortion plus noise (THD + N) Available in 19-ball, 1.74 mm × 2.1 mm, 0.4 mm pitch WLCSP 89.7% system efficiency into 8 Ω at 1 W, VBAT = 3.6 V Output noise: 21.7 μV rms, A-weighted THD + N: 0.025% at 1 kHz, 500 mW output power PSSR: 90 dB at 217 Hz, with dither input 72 dB signal-to-noise ratio (SNR) on output current sensing and 77 dB SNR on voltage sensing Quiescent power consumption: 19.8 mW Pop-and-click suppression Flexible battery monitoring AGC Short-circuit protection for boost and Class-D outputs and thermal protection with automatic recovery Smart power-down when PDM stop condition or no clock input detected DC blocking high-pass filter and static input DC protection for PDM input Selectable ultralow EMI emissions and low latency modes APPLICATIONS Mobile handsets Tablets Portable media players FUNCTIONAL BLOCK DIAGRAM Figure 1. I2S/TDM/ PDM INTERFACE H-BRIDGE (5V) V SENSE R I SENSE Σ-∆ CLASS-D MOD FILTERING MODULATION BOOST (5V) VBAT PGND OUTP OUTN AGND IOVDD SSM4567 DAC_PDM_DAT/ DAC_SDATAI LR_SEL/ ADDR SEL BSTSW BSTSW VBST VBST SCL SDA DAC_PDM_CLK/ BCLK SNS_PDM_DAT/ SNS_SDATAO SNS_PDM_CLK/ FSYNC DAC ADC ADC |
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