SSM4567ACBZ-R7 datasheet(30/52 Pages) AD

30 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 30 of 52

STANDALONE MODE, I2S/TDM INTERFACE

Figure 56. Typical Application Circuit, I2S, Standalone Mode

Description

In this application circuit, the SSM4567 operates in standalone mode, without an I2C master in the system. The I2C address is configured

using the LR_SEL/ADDR pin. The serial data interface is in PCM mode, as configured by the SEL pin.

Pin Configuration

Table 23. Pin Configuration for I2S Software Control Applications, Standalone Mode, I2S/TDM Interface

Hardware Pin

Connection

LR_SEL/ADDR

Pull up to IOVDD with a 47 kΩ resistor to enable standalone mode.

SEL

Connect to IOVDD for PCM mode.

SNS_PDM_CLK/FSYNC

Connect to an external I2S/TDM frame sync clock signal.

DAC_PDM_CLK/BCLK

Connect to an external I2S/TDM bit clock signal.

SNS_PDM_DAT/SNS_SDATAO

Sends current, voltage, and battery sense data in I2S/TDM format to an external IC.

DAC_PDM_DAT/DAC_SDATAI

Receives a serial audio data signal in I2S/TDM format from an external IC.

SCL

Connect to either IOVDD or AGND to select which I2S/TDM audio data slot is sent to the amplifier (see

Table 10).

SDA

Connect to either IOVDD or AGND to select which I2S/TDM audio data slot is sent to the amplifier (see

Table 10).

I2S/TDM/

PDM

INTERFACE

H-BRIDGE

(5V)

SENSE

Σ-Δ

CLASS-D

MOD

FILTERING

MODULATION

BOOST (5V)

OUTP

OUTN

22µF

10µF

1µF

2.2µH

VBAT

AGND

IOVDD

SSM4567

LR_SEL/

ADDR

SEL

BSTSW

IOVDD

47kΩ

BSTSW

VBST

PGND

SCL

SDA

DAC

ADC

IOVDD

VBAT

0.1µF

IOVDD

1µF

DAC_PDM_CLK/

BCLK

SNS_PDM_CLK/

FSYNC

SNS_PDM_DAT/

SNS_SDATAO

DAC_PDM_DAT/

DAC_SDATAI

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