SSM4567ACBZ-R7 datasheet(37/52 Pages) AD

37 / 52 page

Data Sheet

SSM4567

Rev. 0| Page 37 of 52

SERIAL AUDIO INTERFACE CONTROL 1 REGISTER

Address: 0x04, Reset: 0x00, Name: SAI_CTRL_1

Table 30. Bit Descriptions for SAI_CTRL_1

Bits

Bit Name

Settings

Description

Reset

Access

SAI_DRV

Drive Control for Unused BCLK Cycles

0x0

R/W

Unused BCLK cycles on SNS_SDATA are not driven (high-Z)

Unused BCLK cycles on SNS_SDATA are driven low

BCLK_POL

BCLK Polarity

0x0

R/W

Rising Edge of BCLK is used to register SDATA

Falling Edge of BCLK is used to register SDATA

[5:4]

TDM_BCLKS

Number of BCLK cycles per chip in TDM Mode. Any number of BCLK cycles per

FSYNC can be used in stereo modes (I2S/left justified) or in TDM mode with only one

chip. When in TDM mode, with multiple chips on the TDM bus, the number of BCLK

cycles per chip must be defined.

0x0

R/W

32 BCLK cycles per chip in TDM

48 BCLK cycles per chip in TDM

64 BCLK cycles per chip in TDM

FSYNC_MODE

FSYNC Mode Control

0x0

R/W

Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM Modes

High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes

SDATA_FMT

Serial Data Format

0x0

R/W

I2S/Delay by one from FSYNC edge

Left Justified/No delay from FSYNC edge

SAI_MODE

Serial Audio Interface Mode Selection

0x0

R/W

Stereo Modes (I2S, left justified)

TDM/PCM Modes

PDM_MODE

PDM Input and Output Mode

0x0

R/W

Normal Serial Audio Interface Operation

PDM used for input and output

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