SSM4567ACBZ-R7 datasheet(16/52 Pages) AD

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SSM4567

Data Sheet

Rev. 0| Page 16 of 52

Table 6. PDM Timing Parameters

Parameter

Limit

Unit

Description

tMIN

tMAX

tFALL

Clock fall time

tRISE

Clock rise time

tSETUP

Data setup time

tHOLD

Data hold time

Figure 35. PDM Input Data Format

The PDM data is output on both edges of the clock. The current

sense ADC data is output when SNS_PDM_CLK/FSYNC is

high and should be read on the falling edge. The voltage sense

ADC data is output when SNS_PDM_CLK/FSYNC is low and

should be read on the rising edge.

Figure 36. SDATA (DAC_SDATAI/SNS_SDATAO) Output in PDM Mode

By default in PDM mode, PDM pattern control is used for

control information. I2C control can be used instead, but do not

use both at the same time. If PDM pattern control is engaged,

then registers associated with the PDM pattern control do not

function using I2C. Writes to those registers are ignored and

reads do not reflect the current state of the device. For I2C

control, it is best to tie the SEL pin to IOVDD and then set the

PAT_CTRL_EN bit to 0 to disable PDM pattern control before

any other I2C writes or reads are performed. By default, the I2C

device address in PDM mode is 0x34. By setting the

I2C_ADDR_SET bit, the device address can be either 0x34 or

0x35, depending on the state of the LR_SEL/ADDR pin.

PDM PATTERN CONTROL

PDM mode operation has a simple control mechanism that can

set the device for low power states and control functionality.

This is accomplished by sending a repeating 8-bit pattern to the

device. Different patterns set different functionalities.

Any pattern must be repeated a minimum of 128 times. The

device is automatically muted when a pattern is detected so that

a pattern can be set while the device is operational without a

pop/click due to pattern transition. After this minimum

repetition is complete, the pattern can be removed at any time

and the device resumes normal operation.

All patterns except mute and power-down are sticky, in that

after the pattern is sent the functionality of the pattern remains

after the pattern is removed. Mute and power-down are active only

when their respective patterns are being continuously written.

All functionality set via patterns return to its default values after a

clock loss power-down or after the device reset pattern is sent.

Table 7. PDM Watermarking Pattern Control Descriptions

Pattern

Control Description

0xD2

Limiter: enable.

LIM_EN = 01

0xD4

Lower gain mode (3.6 V) with

−6 dBFS).

ANA_GAIN = 0

0xD8

Shared clock operation. Only

DAC_PDM_CLK is needed.

SHARED_CLOCK = 1

0xE1

Ultralow EMI mode.

Edges = 1

0xE2

Low latency mode with

pattern delay (~15 µs latency).

LOW_LATENCY = 01

0xE4

Set DAC to low power mode =

off. PDM_CLK = 128 × fS mode.

DAC_LPM = 0

0xAA

Device reset: place the device

into default configuration

0x66

Mute.

DAC_MUTE = 1

0xAC

Power-down: all blocks off

except for PDM interface.

Normal start-up time.

SPWDN = 1

0xF1

Limiter: 3.7 V battery inflection

point.

VBAT_INF = 010

0xF2

Limiter: 3.3 V battery inflection

point.

VBAT_INF = 110

0xF4

Limiter: 2 V/V VBAT vs. the

limiter slope.

Slope = 01

0xC1

Sense power-up/power-down

toggle.

Toggle value of

BSNS_PWDN,

ISNS_PWDN, and

VSNS_PTWN

0xC2

Limiter: threshold value set to

5.4 V peak.

LIM_THRES = 0110

tHOLD

DATA

DAC_SDATAI

BCLK

DATA

tSETUP

BCLK

FSYNC

SDATA

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