SSM4567ACBZ-R7 datasheet(18/52 Pages) AD

18 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 18 of 52

Figure 38 shows a basic timing diagram of the placements in I2S

mode.

The corresponding registers allow configuration of each data

placement. An input placement (Px_DAC) can carry 24-bit

audio data, 16-bit audio data, or eight zero bits that are used as

padding and ignored. See the Right Justified Data section for

more information about using the 8 zero bits settings. A sense

placement (Px_SNS) can contain 16-bit voltage output data, 16-bit

current output data, 8-bit battery voltage data, 8-bit control

data, alternating 16-bit voltage and current data, 8-bit status

data, 8-bit V/I marker and slot ID data, or 8 zero bits.

For standard I2S mode, the serial input is configured to receive

mono audio data, and the serial output is configured to send

voltage, current, and battery data back to the host device. The

corresponding registers are in Table 9 and the corresponding

timing diagram is in Figure 39.

Table 9. Standard I2S Data Placement Settings

Setting

Description

BCLK_POL

0b0

Rising edge of BCLK is used to latch data

FSYNC_MODE

0b0

FSYNC low corresponds to left data channel

SDATA_FMT

0b0

Data MSB is delayed by one bit clock cycle

SAI_MODE

0b0

Stereo mode

MC_I2S

0b0

Normal I2S operation

P1_DAC

0b00

24-bit audio input data is in input Placement P1

P1_SNS

0b000

16-bit sense voltage is in output Placement P1

P2_SNS

0b001

16-bit sense current is in output Placement P2

P3_SNS

0b010

8-bit battery voltage is in Placement P3

Table 10. PCM Modes Pin Setup List

Control Mode

I2C

Control

Address1

TDM

Slot

Signals Connected To Pins For Modes Listed In The First Three Columns

LR_SEL/ADDR

SCL

SDA

SEL

DAC_PDM_CLK/

BCLK

SNS_PDM_CLK/

FSYNC

I2C

0 (0x34)

AGND

SCL

SDA

IOVDD

Bit clock

Frame sync

1 (0x35)

IOVDD

SCL

SDA

IOVDD

Bit clock

Frame sync

2 (0x36)

Open

SCL

SDA

IOVDD

Bit clock

Frame sync

Standalone

(TDM Interface)

N/A

47 kΩ pull-up

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-up

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-up

IOVDD

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-up

IOVDD

Bit clock

Frame sync

Standalone

(I2S Interface)

N/A

47 kΩ pull-up

Boost power

down (active

low)

Shutdown

(active low)

IOVDD

Frame sync

(intentional swap

of CLK pins, Pin

B3 and Pin C1)

Bit clock

(intentional swap

of CLK pins, Pin B3

and Pin C1)

TDM

N/A

47 kΩ pull-down

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-down

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-down

IOVDD

AGND

IOVDD

Bit clock

Frame sync

N/A

47 kΩ pull-down

IOVDD

Bit clock

Frame sync

N/A means not applicable.

Figure 37. Basic Timing Diagram of Placements in TDM Stream

8 BITS/16 BITS/24 BITS

BCLK

FSYNC

DAC_SDATAI

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