SSM4567ACBZ-R7 datasheet(20/52 Pages) AD

20 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 20 of 52

Each chip on the TDM bus can occupy 32, 48, or 64 BCLK

cycles. This is set with the TDM_BCLKS control register and all

chips on the bus must have the same setting. Up to eight SSM4567

chips can be used on a single TDM bus, but only three unique

I2C device addresses are available. The SSM4567 automatically

determines how many possible chips can be placed on the bus

from the BCLK rate. There is no limit to the total number of

BCLK cycles per FSYNC pulse. In standalone mode, only four

slots can be used because there are only four combinations of

the SDA and SCL pins to choose from (see Table 10).

When not in standlone mode, the slot that each SSM4567 uses

is determined either by the LR_SEL/ADDR pin settings or the

TDM_SLOT control register. By default, the setting is

determined by the state of the LR_SEL/ADDR pin, which

allows the first three slots to be selected. However, it can be

overridden by the TDM_SLOT control register, which allows

eight different slots to be selected.

Table 11. TDM Slot Selection

Device Setting

LR_SEL/ADDR Pin Configuration

TDM Chip 1 Slot Used/Driven

Tied to AGND

TDM Chip 2 Slot Used/Driven

Tied to IOVDD

TDM Chip 3 Slot Used/Driven

Open

The six placement control bits determine placement of input

and output data within each chip slot. Input data to the DAC,

using the DAC_PDM_DAT/DAC_SDATAI pin, can be either

16-bit or 24-bit data or it can be set to read in eight bits and

ignore them. This is useful for right justified data formats where

the first eight bits of the 32 bit clocks are padded zeros. The first

placement register is set to read in eight bits and ignore them.

Then the next placement register is set to read in the 24-bit

audio data.

The output data from the DAC, using the SNS_PDM_DAT/

SNS_SDATAO pin, can be any of the following:

•

16-bit voltage output

•

16-bit current output

•

8-bit battery (VBAT) voltage

•

8-bit control data output

•

Alternating 16-bit voltage and current

•

8-bit status output

•

8-bit V/I marker and slot ID

•

Blank eight bits

It is possible to have as many as six output placements and four

input placements per frame depending on the clock rates.

MULTICHIP I2S OPERATING MODE

A special multichip I2S mode is enabled by setting the MC_I2S

control register (Register 0x05[4]) to 1 when under I2C control.

The TDM_SLOT register (Register 0x05[2:0]) sets the slot where

data is expected and sense data is transmitted. In standalone

mode or when AUTO_SAI = 1, multichip I2S is enabled when

the device is wired for TDM mode (that is, the BCLK and

FSYNC signals are not swapped as they would be for I2S/left

justified operation) except the FSYNC signal has a 50% duty

cycle. The frequency of the FSYNC signal in relation to the

BCLK signal determines if the device is in two-chip or four-

chip mode. If the FSYNC signal consists of one BCLK cycle

pulse, TDM operating mode is active instead.

The multichip I2S interface allows multiple chips to drive a single

I2S bus. Each chip takes control of the bus every two or four

frames (depending on the number of chips placed on the bus),

allowing a maximum of four chips on the bus. Each frame or cycle

of the FSYNC signal must 64 BCLK cycles long. The

LR_SEL/ADDR pin assignments determine the order of control.

Each frame also contains a slot ID code that is appended to the

current data in the frame. This code indicates the slot of the

chip that sent the data for that frame.

The mapping of LR_SEL/ADDR pin assignments to the ID tag

when not in standalone mode is shown in Table 12.

Table 12. Multichip I2S Slot Configuration in SA Mode

ADDR Pin Configuration

Slot No.

ID Tag

Tied to AGND

0001

Tied to IOVDD

0010

Open

0100

The device automatically configures for two-chip or four-chip

depending on the number of detected chips in the bus. For two-

chip operation, the first and second slots must be used. Unused

slots are allowed; however, Slot 1 must always be used. To

enable two-chip operation, the device starts in four-chip

operation and, when it is detected that Slot 3 and Slot 4 are

unused, it switches to two-chip operation.

Table 13 describes the FSYNC and BCLK rates that are

supported in multichip I2S mode.

Table 13. FSYNC and BCLK Rates For Multichip I2S

Sample Rate

Valid Slots

FSYNC Rate

BCLK Rate

32 kHz to 48 kHz

1, 2

2 × fS

(32 kHz to

96 kHz)

128 × fS

(2.048 MHz to

6.144 MHz)

32 kHz to 48 kHz

1, 2, 3, 4

4 × fS

(64 kHz to

128 kHz)

256 × fS

(4.096 MHz to

12.288 MHz)

SYSTEM GAIN

The default analog gain of the SSM4567 maps a 0 dBFS input

level to 5.1 V peak nominally at the amplifier output. This

setting provides optimal gain staging for best noise performance.

A lower analog gain setting that maps a 0 dBFS input level to

3.6 V peak can be set via the ANA_GAIN bit, Register 0x01[0].

There is also digital gain/volume control, Register 0x03, that

provides fine control in 0.375 dB steps from −71.25 dB to +24 dB.

There is one additional step for mute.

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