SSM4567ACBZ-R7 datasheet(49/52 Pages) AD

49 / 52 page

Data Sheet

SSM4567

Rev. 0| Page 49 of 52

PDM CONTROL REGISTER

Address: 0x13, Reset: 0x40, Name: PDM_CTRL

Table 45. Bit Descriptions for PDM_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

PDM_LR_SEL

PDM left/right channel select when external PIN SEL =1

0x0

R/W

select left channel

select right channel

PAT_CTRL_EN

Enable PDM pattern control when external PIN SEL=0

0x1

R/W

Disable PDM pattern control

Enable PDM pattern control

RESERVED

Reserved.

0x0

R/W

I2C_ADDR_SET

Setting the I2C Address in PDM mode when external PIN SEL = 0

0x0

R/W

I2C Address is fixed to 0x34 in PDM mode

I2C Address determined by LR_SEL/ADDR pin in PDM mode (LR_SEL/ADDR = 0,

Address = 0x34; LR_SEL/ADDR = 1, Address = 0x35)

[3:2]

LOW_LATENCY

Low latency Mode

0x0

R/W

Normal Mode

Low latency Mode, delay about 15 µs

Low latency Mode, delay about 5 µs

SHARED_CLOCK

Only DAC_PDM_CLK is needed

0x0

R/W

Do not share

DAC_PDM_CLK is shared with SNS_PDM_CLK

SEL_VBAT

Select VBAT to output

0x0

R/W

output sense voltage in PDM mode

Output sense battery voltage (VBAT) in PDM mode

MCLK RATIO SETTING REGISTER

Address: 0x14, Reset: 0x11, Name: MCLK_RATIO

SSM4567ACBZ-R7 Datenblatt(PDF) 49 Page - Analog Devices

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