ADS131M08IPBSR datasheet(22/118 Pages) TI2

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8.3.5 Clocking and Power Modes

The master clock can either be sourced externally to the CLKIN pin or generated internally using the onboard

oscillator that requires a crystal connected between the XTAL1/CLKIN and XTAL2 pins.

For optimal

performance, the modulator sampling clock must be synchronous with the serial data clock (SCLK). The

modulator sampling clock is derived from the master clock, which means the master clock must be synchronous

with SCLK. Therefore, for best performance, supply a master clock to CLKIN and make sure data retrieval is

synchronous to the clock signal at CLKIN. When not in use, turn the internal oscillator off to save power.

The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-

resolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits

scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow

the guidance provided in the Recommended Operating Conditions table corresponding to the intended power

mode in order for the device to perform according to the specification.

8.3.6 ΔΣ Modulator

The ADS131M08 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density

modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times

greater than the output data rate. The modulator frequency, fMOD, of the ADS131M08 is equal to half the master

clock frequency, that is, fMOD = fCLKIN / 2.

The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a

means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency

domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital

decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization

noise, allowing the device to provide excellent dynamic range.

8.3.7 Digital Filter

The ΔΣ modulator bit-stream feeds into a digital filter. The digital filter is a linear phase, finite impulse response

(FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital

filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated

and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output data rate

(fDATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

OSR = fMOD / fDATA

(5)

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. There are OSR settings in the

ADS131M08, allowing different data rate settings for any given master clock frequency. Table 8-2 lists the OSR

settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned.

The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the

filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth

results in lower noise whereas higher bandwidth results in higher noise. See Table 7-1 for the noise

specifications for various OSR settings.

ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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