ADS131M08IPBSR datasheet(46/118 Pages) TI2

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8.5.2 Synchronization

Synchronization can be performed by the host to ensure the ADC conversions are synchronized to an external

event. For example, synchronization can realign the data capture to the expected timing of the host if a glitch on

the clock causes the host and device to become out of synchronization.

Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN

period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its

internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin if

configured to assert with a phase calibration setting of 0b. If the negative edge on SYNC/RESET aligns with the

internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If there is

misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse.

Conversions are immediately restarted when the SYNC/RESET pin is toggled in global-chop mode.

The phase calibration settings on all channels are retained during synchronization. Thus, channels with non-zero

phase calibration settings generate conversion results less than a data rate period after the synchronization

event occurs. However, the results can be corrupted and are not settled until the respective channels have at

least three conversion cycles for the sinc3 filter to settle.

ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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ADS131M08IPBSR Datenblatt(PDF) 46 Page - Texas Instruments