ADS131M08IPBSR datasheet(41/118 Pages) TI2

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Figure 8-20 depicts an example of how to collect data after a period of the ADC running, but where no data are

being retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the

ADS131M08 output data with the host.

DRDY

SCLK

DOUT

CRC

Data

Hi-Z

Status

CRC

Data

Time where data is

not being read

SYNC Pulse

SYNC / RESET

Figure 8-20. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin

Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by

reading two samples in quick succession. Figure 8-21 depicts this method. This example shows when the

DRDY_FMT bit in the MODE register is set to 0b indicating DRDY is a level output. There is a very narrow pulse

on DRDY immediately after the first set of data are shifted out of the device. This pulse may be too narrow for

some microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the

second data set after the first data set. The host operates synchronous to the device after the second word is

read from the device.

DRDY

SCLK

DOUT

CRC

Data

Hi-Z

Status

CRC

Data

Status

CRC

Data

Time where data is

not being read

Narrow DRDY Pulse

Data is read a

second time

Figure 8-21. Collecting Data After a Pause in Data Collection by Reading Data Twice

8.5.1.10 Commands

Table 8-11 contains a list of all valid commands, a short description of their functionality, their binary command

word, and the expected response that appears in the following frame.

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ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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