ADS131M08IPBSR datasheet(95/118 Pages) TI2

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9.1.7 Troubleshooting

Table 9-1 lists common issues faced when designing with the ADS131M08 and the corresponding solutions. This

list is not comprehensive.

Table 9-1. Troubleshooting Common Issues Using the ADS131M08

ISSUE

POSSIBLE ROOT CAUSE

POSSIBLE SOLUTION

The DRDY pin is toggling at half the

expected frequency.

ADC conversion data are not being read. The

two-deep ADC data FIFO overflows and

triggers DRDY one time every two ADC data

periods.

Read data after each DRDY falling edge after

following the recommendations given in the

Collecting Data for the First Time or After a

Pause in Data Collection section.

The F_RESYNC bit is set in the STATUS

word even though this bit was already

cleared.

The SYNC/RESET pin is being toggled

asynchronously to CLKIN.

The SYNC/RESET pin functions as a

constant synchronization check, rather than a

convert start pin. See the Synchronization

section for more details on the intended

usage of the SYNC/RESET pin.

The same ADC conversion data are output

twice before changing.

The entire frame is not being sent to the

ADC. The ADC does not recognize data as

being read.

Read all data words in the output data frame,

including those for channels that are

disabled.

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ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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ADS131M08IPBSR Datenblatt(PDF) 95 Page - Texas Instruments