ADS131M08IPBSR datasheet(45/118 Pages) TI2

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8.5.1.10.8 WREG (011a aaaa annn nnnn)

The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the

command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing

and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be

written immediately following the command word. Write the intended contents of each register into individual

words, MSB aligned.

If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as they

are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a

The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map

address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them.

The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm

where mmm mmmm is the number of registers actually written minus one. This number can be checked by the

host against nnn nnnn to ensure the expected number of registers are written.

Figure 8-25 shows a typical WREG sequence. In this example, the number of registers to write is larger than the

number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC

word. Ensure all of the ADC data and output CRC are shifted out during each transaction where new data are

available. Therefore, the frame must be extended beyond the number of words required to send the register data

in some cases.

DRDY

SCLK

DIN

DOUT

Channel 0 Data

Channel 1 Data

Channel 7 Data

CRC

Response

Hi-Z

'RQ¶W &DUH

Channel 0 Data

Response

WREG

st UHJLVWHU¶V

data

Command

CRC

nd UHJLVWHU¶V

data

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

N-1

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

CRC

Hi-Z

Figure 8-25. Writing Registers

8.5.1.11 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and

no ADC data are being output by the device. Read out all of the expected output data words from each sample

period if the ADCs are enabled. Reading all of the data output with each frame ensures predictable DRDY pin

behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the

First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from

when the ADCs were last enabled.

A short frame is not possible when using the RESET command. A full frame must be provided for a device reset

to take place when providing the RESET command.

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ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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