ADS131M08IPBSR datasheet(73/118 Pages) TI2

Teilenummer	ADS131M08IPBSR

Bauteilbeschribung	ADS131M08 8-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC

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8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.

Return to the Summary Table.

Figure 8-50. CH3_CFG Register

PHASE3[9:2]

R/W-0000000000b

PHASE3[1:0]

RESERVED

DCBLK3_DIS

MUX3

R/W-0000000000b

R-000b

R/W-0b

R/W-00b

Table 8-38. CH3_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:6

PHASE3[9:0]

R/W

0000000000

Channel 3 phase delay

Phase delay in modulator clock cycles provided in two's complement

format. See Table 8-5 for details.

5:3

RESERVED

000b

Reserved

always reads 00000000b

DCBLK3_DIS

R/W

Channel 3 DC Block filter disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0

MUX3

R/W

00b

Channel 3 input selection

00b = AIN3P and AIN3N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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