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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADS131M08IPBSR Datenblatt(PDF) 53 Page - Texas Instruments |
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ADS131M08IPBSR Datenblatt(HTML) 53 Page - Texas Instruments |
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53 / 118 page  8.6.3 MODE Register (Address = 02h) [reset = 0510h] The MODE register is shown in Figure 8-28 and described in Table 8-16. Return to the Summary Table. Figure 8-28. MODE Register 15 14 13 12 11 10 9 8 RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0] R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b 7 6 5 4 3 2 1 0 RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b Table 8-16. MODE Register Field Descriptions Bit Field Type Reset Description 15:14 RESERVED R/W 00b Reserved always reads 00b 13 REG_CRC_EN R/W 0b Register Map CRC enable 0b = Disabled (default) 1b = Enabled 12 RX_CRC_EN R/W 0b SPI input CRC enable 0b = Disabled (default) 1b = Enabled 11 CRC_TYPE R/W 0b SPI and register map CRC type 0b = 16-bit CCITT (default) 1b = 16-bit ANSI 10 RESET R/W 1b Reset write 0b to clear this bit in the STATUS register 0b = No reset 1b = Reset happened (default by definition) 9:8 WLENGTH[1:0] R/W 01b Data word length selection 00b = 16 bits 01b = 24 bits (default) 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension 7:5 RESERVED R/W 000b Reserved always write 000b 4 TIMEOUT R/W 1b SPI Timeout enable 0b = Disabled 1b = Enabled (default) 3:2 DRDY_SEL[1:0] R/W 00b DRDY pin signal source selection 00b = Most lagging enabled channel (default) 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: ADS131M08 |
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