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ADS131M08IPBSR Datenblatt(PDF) 82 Page - Texas Instruments |
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ADS131M08IPBSR Datenblatt(HTML) 82 Page - Texas Instruments |
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82 / 118 page ![]() 8.6.40 CH6_CFG Register (Address = 27h) [reset = 0000h] The CH6_CFG register is shown in Figure 8-65 and described in Table 8-53. Return to the Summary Table. Figure 8-65. CH6_CFG Register 15 14 13 12 11 10 9 8 PHASE6[9:2] R/W-0000000000b 7 6 5 4 3 2 1 0 PHASE6[1:0] RESERVED DCBLK6_DIS MUX6 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-53. CH6_CFG Register Field Descriptions Bit Field Type Reset Description 15:6 PHASE6[9:0] R/W 0000000000 b Channel 6 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b 2 DCBLK6_DIS R/W 0b Channel 6 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX6 R/W 00b Channel 6 input selection 00b = AIN6P and AIN6N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com 82 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 |
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