ADS131M08IPBSR datasheet(90/118 Pages) TI2

90 / 118 page

9.1.3 Minimum Interface Connections

Figure 9-2 depicts how the ADS131M08 can be configured for the minimum number of interface pins. This

configuration is useful when using data isolation to minimize the number of isolation channels required or when

the microcontroller (MCU) pins are limited.

The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a local

LVCMOS output device. Tie the SYNC/RESET pin to DVDD in hardware if unused. The DRDY pin can be left

floating if unused. Connect either SYNC/RESET or DRDY to the MCU to ensure the MCU stays synchronized to

ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to determine the sample

period rather than forcing synchronization using the SYNC/RESET pin or monitoring the DRDY pin.

Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if the SYNC/

RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS131M08 is the only device on the

SPI bus. Ensure the data input and output CRC are enabled and are used to guard against faulty register reads

and writes if CS is tied low permanently.

See the Clocking and Power Modes section for more information regarding synchronization and how to

implement the clocking scheme for optimized device performance.

MCU

Device

Local

Oscillator

DVDD

DGND

CLKOUT

CLKIN

GPIO

SYNC/RESET

GPIO

DRDY

SCLK

MOSI

DIN

MISO

DOUT

Figure 9-2. Minimum Connections Required to Operate the ADS131M08

ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

www.ti.com

Submit Document Feedback

Product Folder Links: ADS131M08

ADS131M08IPBSR Datenblatt(PDF) 90 Page - Texas Instruments