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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADS131M08IPBSR Datenblatt(PDF) 23 Page - Texas Instruments |
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ADS131M08IPBSR Datenblatt(HTML) 23 Page - Texas Instruments |
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23 / 118 page  Table 8-2. OSR Settings and Data Rates for Nominal Master Clock Frequencies POWER MODE NOMINAL MASTER CLOCK FREQUENCY fMOD OSR OUTPUT DATA RATE HR 8.192 MHz 4.096 MHz 128 32 kSPS 256 16 kSPS 512 8 kSPS 1024 4 kSPS 2048 2 kSPS 4096 1 kSPS 8192 500 SPS 16384 250 SPS LP 4.096 MHz 2.048 MHz 128 16 kSPS 256 8 kSPS 512 4 kSPS 1024 2 kSPS 2048 1 kSPS 4096 500 SPS 8192 250 SPS 16384 125 SPS VLP 2.048 MHz 1.024 MHz 128 8 kSPS 256 4 kSPS 512 2 kSPS 1024 1 kSPS 2048 500 SPS 4096 250 SPS 8192 125 SPS 16384 62.5 SPS 8.3.7.1 Digital Filter Implementation Figure 8-3 shows the digital filter implementation of the ADS131M08. The modulator bit-stream feeds two parallel filter paths, a sinc3 filter, and a fast-settling filter path. Modulator Bitstream Sinc 3 Regular Filter Fast-Settling Filter Sinc 1 Averager (OSR>1024) Global Chop Logic PHASEx[9:0] PGA_GAINx[2:0] 265 ” 1024 Power-up or Reset MUX MUX 1 0 1 0 Calibration Logic, Gain scaling OSR = 1024 OSR[2:0] OSR[2:0] Phase Delay Figure 8-3. Digital Filter Implementation 8.3.7.1.1 Fast-Settling Filter At power-up or after a device reset, the ADS131M08 selects the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1). After two conversions, the device switches to and remains in the sinc3 filter path until the next time the device is reset or powered cycled. www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: ADS131M08 |
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