ADS131M08IPBSR datasheet(98/118 Pages) TI2

98 / 118 page

RHI is 300 kΩ and RLO is 750 Ω in this design. For a mains voltage of 240 V (as measured between the line and

neutral), the input signal to the voltage ADC has a voltage swing of ±256 mV (182 mVRMS) based on Equation 11

and the selected resistor values. This voltage is well within the ±1.2-V input voltage range that can be sensed by

the ADS131M08 for the selected PGA gain value of 1 that is used for the voltage channels.

9.2.2.2 Current Measurement Front-End

The analog front-end for current inputs is different from the analog front-end for the voltage inputs. Figure 9-7

shows the analog front-end used for a current channel.

FILT

AINxP

AINxN

Live

Figure 9-7. Current Measurement Front-End

The analog front-end for current consists of burden resistors for the current transformers (RB) and an RC low-

pass filter (RFILT and CFILT) that functions as an antialias filter.

Two identical burden resistors in series are used with the common point being connected to GND instead of

using one burden resistor for best THD performance. This split-burden resistor configuration ensures that the

waveforms fed to the positive and negative terminals of the ADC are 180 degrees out-of-phase with each other,

which provides the best THD results with this ADC. The total burden resistance is selected based on the current

range used and the turns ratio specification of the CT (this design uses CTs with a turns ratio of 2000). The total

value of the effective burden resistor (2RB) for this design is 12.98 Ω.

Equation 12 shows how to calculate the range of differential voltages fed to the current ADC channel for a given

maximum current, CT turns ratio, and burden resistor value.

ADC

RMS

2 N

(12)

Based on the maximum RMS current of 100 A, a CT turns ratio NCT of 2000, and an effective burden resistor

2RB between AINxP and AINxN of 12.98 Ω for this design, the input signal to the current ADC has a voltage

swing of ±918 mV maximum (649 mVRMS) when the maximum current rating of the meter (100 A) is applied. This

±918-mV maximum input voltage is well within the ±1.2-V input range of the device for the selected PGA gain of

1 that is used for the current channels.

9.2.2.3 ADC Setup

The ADS131M08 receives its clock from the MCU in this design. The ADS131M08 is configured in HR mode and

the MCU provides an 8.192-MHz master clock, which is within the allowable clock frequency range for HR mode.

The MCU SPI port that is used to communicate with the ADS131M08 is configured to CPOL = 0 and CPHA = 1.

The SPI clock frequency is configured to be 8.192 MHz so that all conversion data can be shifted out of the

device successfully within the sample period. When powered on, the MCU configures the ADS131M08 registers

with the following settings using SPI register writes.

• GAIN1 and GAIN2 register settings: PGA gain of 1 is used for all ADC channels.

• CHx_CNG register settings (where x is the channel number): All ADC channel inputs are connected to the

external ADC pins and the channel phase delay set to 0 for each channel. The channel phase setting can

also be configured in this register. This design uses an integer number of output samples for phase

calibration so the processing is done in software completely.

• CLOCK register settings: OSR = 512, all channels enabled, and HR mode.

ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

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