ADS131M08IPBSR datasheet(29/118 Pages) TI2

29 / 118 page

Table 8-6. GCALn[23:0] Bit Mapping

GCALn[23:0] VALUE

GAIN CALIBRATION FACTOR

000000h

000001h

1.19 × 10–7

800000h

FFFFFEh

2 – 2.38 × 10–7

FFFFFFh

2 – 1.19 × 10–7

The calibration registers do not need to be enabled because they are always in use. The OCALn[23:0] bits have

a default value of 000000h resulting in no offset correction. Similarly, the GCALn[23:0] bits default to 800000h

resulting in a gain calibration factor of 1.

Figure 8-12 depicts a block diagram illustrating the mechanics of the calibration registers on one channel of the

ADS131M08.

Digital

Filter

To Interface

OCALn[23:0]

GCALn[23:0]

Modulator

Figure 8-12. Calibration Block Diagram

8.3.12 Communication Cyclic Redundancy Check (CRC)

The ADS131M08 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate

SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all

words in the SPI frame where the CRC is enabled, including padded bits in a 32-bit word size.

CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE

CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not match.

The device does not execute any commands, except for the WREG command, if the input CRC check fails. A

WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit in the

STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the frame

where the CRC error occurred is that of a NULL command, which means the STATUS register plus the

conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is

output.

The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the

data if the output CRC is not used.

There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting

determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE

bit in the MODE register. Table 8-7 lists the details of the two CRC types.

The seed value of the CRC calculation is FFFFh.

Table 8-7. CRC Types

CRC TYPE

POLYNOMIAL

BINARY POLYNOMIAL

CCITT CRC

x16 + x12 + x5 + 1

0001 0000 0010 0001

ANSI CRC

x16 + x15 + x2 + 1

1000 0000 0000 0101

www.ti.com

ADS131M08

SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021

Submit Document Feedback

Product Folder Links: ADS131M08

ADS131M08IPBSR Datenblatt(PDF) 29 Page - Texas Instruments

ADS131M08IPBSR Datenblatt(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL