 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
ADS131M08IPBSR Datenblatt(PDF) 28 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADS131M08IPBSR Datenblatt(HTML) 28 Page - Texas Instruments |
|
|
28 / 118 page  The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed, the device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128 and the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the device sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR setting. Table 8-5 gives the range of phase calibration settings for various OSR settings. Table 8-5. Phase Calibration Setting Limits for Different OSR Settings OSR SETTING PHASE OFFSET RANGE (tMOD) PHASEn[9:0] BITS RANGE 128 –64 to 63 11 1100 0000b to 00 0011 1111b 256 –128 to 127 11 1000 0000b to 00 0111 1111b 512 –256 to 255 11 0000 0000b to 00 1111 1111b 1024 –512 to 511 10 0000 0000b to 01 1111 1111b 2048 –512 to 511 10 0000 0000b to 01 1111 1111b 4096 –512 to 511 10 0000 0000b to 01 1111 1111b 8192 –512 to 511 10 0000 0000b to 01 1111 1111b 16384 –512 to 511 10 0000 0000b to 01 1111 1111b Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048: • Create a phase shift corresponding to an integer number of sample periods by modifying the indices between channel data in software • Use the phase calibration function of the ADS131M08 to create the remaining fractional sample period phase shift For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output data stream in the host software. Make the remaining 0.25 sample adjustment using the ADS131M08 phase calibration function. The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the Data Ready (DRDY) section for more details regarding how phase calibration affects the DRDY signal. 8.3.11 Calibration Registers The calibration registers allow for the automatic computation of calibrated ADC conversion results from pre- programmed values. The host can rely on the device to automatically correct for system gain and offset after the error correction terms are programmed into the corresponding device registers. The measured calibration coefficients must be store in external non-volatile memory and programmed into the registers each time the ADS131M08 powers up because the ADS131M08 registers are volatile. The offset calibration registers are used to correct for system offset error, otherwise known as zero error. Offset error corresponds to the ADC output when the input to the system is zero. The ADS131M08 corrects for offset errors by subtracting the contents of the OCALn[23:0] register bits in the CHn_OCAL_MSB and CHn_OCAL_LSB registers from the conversion result for that channel before being output. There are separate CHn_OCAL_MSB and CHnOCAL_LSB registers for each channel, which allows separate offset calibration coefficients to be programmed for each channel. The contents of the OCALn[23:0] bits are interpreted by the device as 24-bit two's complement values, which is the same format as the ADC data. The gain calibration registers are used to correct for system gain error. Gain error corresponds to the deviation of gain of the system from its ideal value. The ADS131M08 corrects for gain errors by multiplying the ADC conversion result by the value given by the contents of the GCALn[23:0] register bits in the CHn_GCAL_MSB and CHn_GCAL_LSB registers before being output. There are separate CHn_GCAL_MSB and CHn_GCAL_LSB registers for each channel, which allows separate gain calibration coefficients to be programmed for each channel. The contents of the GCALn[23:0] bits are interpreted by the device as 24-bit unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 223). Table 8-6 describes the relationship between the GCALn[23:0] bit values and the gain calibration factor. ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
