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ADS131M08IPBSR Datenblatt(PDF) 10 Page - Texas Instruments

Teilenummer ADS131M08IPBSR
Bauteilbeschribung  ADS131M08 8-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC
PDF  118 Pages
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Hersteller  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS131M08IPBSR Datenblatt(HTML) 10 Page - Texas Instruments

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6.6 Timing Requirements
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
MIN
NOM
MAX
UNIT(1)
1.65 V ≤ DVDD ≤ 2.0 V
tw(CLL)
Pulse duration, CLKIN low
49
ns
tw(CLH)
Pulse duration, CLKIN high
49
ns
tc(SC)
SCLK period
64
ns
tw(SCL)
Pulse duration, SCLK low
32
ns
tw(SCH)
Pulse duration, SCLK high
32
ns
td(CSSC)
Delay time, first SCLK rising edge after CS falling edge
16
ns
td(SCCS)
Delay time, CS rising edge after final SCLK falling edge
10
ns
tw(CSH)
Pulse duration, CS high
20
ns
tsu(DI)
Setup time, DIN valid before SCLK falling egde
5
ns
th(DI)
Hold time, DIN valid after SCLK falling edge
10
ns
tw(RSL)
Pulse duration, SYNC/RESET low to generate device reset
2048
tCLKIN
tw(SYL)
Pulse duration, SYNC/RESET low for synchronization
1
2047
tCLKIN
tsu(SY)
Setup time, SYNC/RESET valid before CLKIN rising edge
10
ns
2.7 V ≤ DVDD ≤ 3.6 V
tw(CLL)
Pulse duration, CLKIN low
49
ns
tw(CLH)
Pulse duration, CLKIN high
49
ns
tc(SC)
SCLK period
40
ns
tw(SCL)
Pulse duration, SCLK low
20
ns
tw(SCH)
Pulse duration, SCLK high
20
ns
td(CSSC)
Delay time, first SCLK rising edge after CS falling edge
16
ns
td(SCCS)
Delay time, CS rising edge after final SCLK falling edge
10
ns
tw(CSH)
Pulse duration, CS high
15
ns
tsu(DI)
Setup time, DIN valid before SCLK falling egde
5
ns
th(DI)
Hold time, DIN valid after SCLK falling edge
10
ns
tw(RSL)
Pulse duration, SYNC/RESET low to generate device reset
2048
tCLKIN
tw(SYL)
Pulse duration, SYNC/RESET low for synchronization
1
2047
tCLKIN
tsu(SY)
Setup time, SYNC/RESET valid before CLKIN rising edge
10
ns
(1)
tCLKIN = 1/fCLKIN
6.7 Switching Characteristics
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT(1)
1.65 V ≤ DVDD ≤ 2.0 V
tp(CSDO)
Propagation delay time, CS falling
edge to DOUT driven
50
ns
tp(SCDO)
Progapation delay time, SCLK rising
edge to valid new DOUT
32
ns
tp(CSDOZ)
Propagation delay time, CS rising
edge to DOUT high impedace
75
ns
tw(DRH)
Pulse duration, DRDY high
4
tCLKIN
tw(DRL)
Pulse duration, DRDY low
4
tCLKIN
SPI timeout
32768
tCLKIN
tPOR
Power-on-reset time
Measured from supplies at 90% to
first DRDY rising edge
250
μs
ADS131M08
SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021
www.ti.com
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Product Folder Links: ADS131M08



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