RZSLASHT1 datasheet(108/139 Pages) RENESAS

108 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 108 of 139

Jun. 30, 2025

RZ/T1 Group

2. Electrical Characteristics

2.4.5.10

SPIBSC Timing

Note 1. tPAcyc: PCLKA cycle

Table 2.28

SPIBSC Timing

Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF

Item

Symbol

min

max

Unit*1

Test

Conditions

SPIBSC

SPBCLK clock cycle

tSPBcyc

4080

tPAcyc

Figure 2.57

SPBCLK high level pulse width

tSPBWH

0.45

0.55

tSPBcyc

SPBCLK low level pulse width

tSPBWL

0.45

0.55

tSPBcyc

Data input setup time

tSU

3.5

―

Figure 2.58,

Figure 2.59,

Figure 2.60

Data input hold time

0.5

―

SSL setup time

tLEAD

1 × tSPBcyc – 3

8 × tSPBcyc

SSL hold time

tLAG

1.5 × tSPBcyc

8.5 × tSPBcyc + 3

Continuous transfer delay time

tTD

tSPBcyc

Data output delay time

tOD

―3.6

Data output hold time

tOH

-1

―

Data output buffer on time

tBON

―

3.6

Figure 2.61,

Figure 2.62,

Figure 2.63

Data output buffer off time

tBOFF

-7

Figure 2.57

SPIBSC Clock Timing

tSPBcyc

SPBCLK

output

tSPBWL

tSPBWH

RZ/T1 Datenblatt(PDF) 108 Page - Renesas Technology Corp

RZ/T1 Datenblatt(HTML) 108 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL