SPRUG18 datasheet(120/214 Pages) TI

120 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.8.3

PLL1 Controller Register Descriptions

This section provides a description of the PLL1 controller registers. For details on the operation of the PLL

controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)

Controller User's Guide (literature number SPRUG09).

NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.

Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked

Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.

Only those registers documented in this section are supported. Furthermore, only the bits within the

registers described here are supported. You should not write to any reserved memory location or change

the value of reserved bits.

7.8.3.1

PLL1 Control Register

The PLL control register (PLLCTL) is shown in Figure 7-11 and described in Table 7-25.

Reserved

R-0

PLL

Reserved

Rsvd

Reserved

PLLRST

Rsvd

PLLEN

PWRDN

R-0

R/W-0

R-1

R/W-0

R/W-1

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]

Table 7-25. PLL1 Control Register (PLLCTL) Field Descriptions

Bit

Field

Value

Description

31:8

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Reserved

Reserved. Writes to this register must keep this bit as 0.

Reserved

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

5:4

Reserved

Reserved. Writes to this register must keep this bit as 0.

PLLRST

PLL reset bit

PLL reset is released

PLL reset is asserted

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

PLLPWRDN

PLL power-down mode select bit

PLL is operational

PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off

PLLEN

PLL enable bit

Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from

input reference clock.

PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are

divided down from PLL output.

120

Peripheral Information and Electrical Specifications

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