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SPRUG18 Datenblatt(PDF) 121 Page - Texas Instruments

Teilenummer SPRUG18
Bauteilbeschribung  TMS320C6474 Multicore Digital Signal Processor
PDF  214 Pages
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SPRUG18 Datenblatt(HTML) 121 Page - Texas Instruments

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TMS320C6474
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SPRS552H
– OCTOBER 2008 – REVISED APRIL 2011
7.8.3.2
PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-26. The PLLM
register defines the input reference clock frequency multiplier.
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Table 7-26. PLL Multiplier Control Register (PLLM) Field Descriptions(1)
Bit
Field
Value
Description
31:5
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0
PLLM
PLL multiplier bits. Defines the input reference clock frequency multiplier.
0h
Bypass
3h
x4 multiplier rate
4h
x5 multiplier rate
.
.
.
.
.
.
1Eh
x31 multiplier rate
1Fh
x32 multiplier rate
(1)
For more information, see Section 7.8.4.
Copyright
© 2008–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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