SPRUG18 datasheet(123/214 Pages) TI

123 / 214 page

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.8.3.4

PLL Controller Divider 13 Register

The PLL controller divider 13 register (PLLDIV13) is shown in Figure 7-14 and described in Table 7-28.

Reserved

R-0

D13EN

Reserved

RATIO

R/W-1

R-0

R/W-3

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-14. PLL Controller Divider 13 Register (PLLDIV13) [Hex Address: 029A 0184]

Table 7-28. PLL Controller Divider 13 Register (PLLDIV13) Field Descriptions

Bit

Field

Value

Description

31:16

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no

effect.

D13EN

Divider 13 enable bit.

Divider 13 is disabled. No clock output.

Divider 13 is enabled.

14:5

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no

effect.

4:0

RATIO

0-1Fh

Divider ratio bits.

0h-31h

÷1 to ÷32. Divide frequency by 1 to divide frequency by 32.

32h-1Fh

Reserved, do not use.

Peripheral Information and Electrical Specifications

123

Submit Documentation Feedback

Product Folder Link(s) :TMS320C6474

SPRUG18 Datenblatt(PDF) 123 Page - Texas Instruments

SPRUG18 Datenblatt(HTML) 123 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL