SPRUG18 datasheet(140/214 Pages) TI

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CLKS

chip_clks

CPU/ ,

Where

=8to32

InternalClockSource

CPU/6

DEVCFG.CLKS0/1

CLKSRG

CLKSM

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.12 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

•

Full-duplex communication

•

Double-buffered data registers, which allow a continuous data stream

•

Independent framing and clocking for receive and transmit

•

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

External shift clock or an internal, programmable frequency shift clock for data transfer

•

SPI operation in master mode only

For more detailed information on the McBSP peripheral, see the TMS320C6474 DSP Multichannel

Buffered Serial Port (McBSP) Reference Guide (literature number SPRUG17).

7.12.1 McBSP Device-Specific Information

The CLKS signal for MCBSP0 and MCBSP1 can be sourced from an external pin or by PLL Controller 1.

For details, see Section 7.8. If the clock from the PLL Controller 1 is used, the clock is shared between the

two McBSPs.Figure 7-27 shows the sample rate generator clock (CLKSRG) selection logical diagram.

For more details, see SYSCLK11 description in Section 7.8.1.1.

Figure 7-27. Sample Rate Generator Clock (CLKSRG)

7.12.2 McBSP Peripheral Register Descriptions

The memory map of the McBSP 0 registers is shown in Table 7-42.

Table 7-42. McBSP 0 Registers

HEX ADDRESS

ACRONYM

028C 0000

DRR0

McBSP0 Data Receive Register via Configuration Bus.

Note: The CPU and EDMA3 controller can only read this register; they can not

write to it.

3000 0000

DRR0

McBSP0 Data Receive Register via EDMA3 Bus

028C 0004

DXR0

McBSP0 Data Transmit Register via Configuration Bus

3000 0010

DXR0

McBSP0 Data Transmit register via EDMA bus

028C 0008

SPCR0

McBSP0 Serial Port Control Register

028C 000C

RCR0

McBSP0 Receive Control Register

028C 0010

XCR0

McBSP0 Transmit Control Register

028C 0014

SRGR0

McBSP0 Sample Rate Generator Register

028C 0018

MCR0

McBSP0 Multichannel Control Register

028C 001C

RCERE00

McBSP0 Enhanced Receive Channel Enable Register 0 Partition A/B

028C 0020

XCERE00

McBSP0 Enhanced Transmit Channel Enable Register 0 Partition A/B

028C 0024

PCR0

McBSP0 Pin Control Register

140

Peripheral Information and Electrical Specifications

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