SPRUG18 datasheet(142/214 Pages) TI

142 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.12.3 McBSP Electrical Data/Timing

Table 7-44. Timing Requirements for McBSP(1)

(see Figure 7-28)

NO.

MIN

MAX

UNIT

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

10P(2)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

0.5t c(CKRX)-1

(2)

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR int

CLKR ext

1.3

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR int

CLKR ext

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR int

CLKR ext

0.9

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR int

CLKR ext

3.1

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKR int

CLKR ext

1.3

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKR int

CLKR ext

(1)

P = 1/CPU Clock in ns.

(2)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty

cycles.

142

Peripheral Information and Electrical Specifications

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