SPRUG18 datasheet(138/214 Pages) TI

138 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.11.3 I2C Electrical Data/Timing

Table 7-40. Timing Requirements for I2C Timings(1)

(see Figure 7-25)

NO.

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

tc(SCL)

Cycle time, SCL

2.5

μs

tsu(SCLH-SDAL)

Setup time, SCL high before SDA low (for a

4.7

0.6

μs

repeated START condition)

th(SCLL-SDAL)

Hold time, SCL low after SDA low (for a

0.6

μs

START and a repeated START condition)

tw(SCLL)

Pulse duration, SCL low

4.7

1.3

μs

tw(SCLH)

Pulse duration, SCL high

0.6

μs

tsu(SDAV-SDLH)

Setup time, SDA valid before SCL high

250

100(2)

μs

th(SDA-SDLL)

Hold time, SDA valid after SCL low (for I2C

0(3)

0.9(4)

μs

bus

™ devices)

tw(SDAH)

Pulse duration, SDA high between STOP and

4.7

1.3

μs

START conditions.

tr(SDA)

Rise time, SDA

1000

20 + 0.1Cb

300

tr(SCL)

Rise time, SCL

1000

20 + 0.1Cb

300

tf(SDA)

Fall time, SDA

300

20 + 0.1Cb

300

tf(SCL)

Fall time, SCL

300

20 + 0.1Cb

300

tsu(SCLH-SDAH)

Setup time, SCL high before SDA high (for

0.6

μs

STOP condition)

tw(SP)

Pulse duration, spike (must be suppressed)

(5)

Capacitive load for each bus line

400

(1)

The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2)

A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement, tsu(SDA-SCLH)≥ 250 ns, must then be

met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line, Tr max + Tsu(SDA-SCLH) = 1000 + 250 + 1250 ns

(according to the standard-mode I2C-bus specification), before the SCL line is released.

(3)

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4)

The maximum, th(SDA-SCLL), has only to be met if the device does not stretch the low period, tw(SCLL), of the SCL signal.

(5)

Cb = total capacitance of one bus line, in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Figure 7-25. I2C Receive Timings

138

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s) :TMS320C6474

SPRUG18 Datenblatt(PDF) 138 Page - Texas Instruments

SPRUG18 Datenblatt(HTML) 138 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL