WM8948ECSSLASHR datasheet(70/189 Pages) WOLFSON

70 / 189 page

WM8948

Production Data

PD, May 2011, Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R42 (2Ah)

Output ctrl

SPKR_DISCH

Discharges SPKOUTR output via

approx 4k resistor

0 = Not active

1 = Actively discharging SPKOUTR

SPKL_DISCH

Discharges SPKOUTL output via

approx 4k resistor

0 = Not active

1 = Actively discharging SPKOUTL

LINER_DISCH

Discharges LINEOUTR output via

approx 4k resistor

0 = Not active

1 = Actively discharging LINEOUTR

LINEL_DISCH

Discharges LINEOUTL output via

approx 4k resistor

0 = Not active

1 = Actively discharging LINEOUTL

Table 43 Output Discharge Control

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data into the WM8948 and outputting ADC data

from it. It uses four pins:



ADCDAT: ADC data output



DACDAT: DAC data input



LRCLK: DAC and ADC data alignment clock



BCLK: Bit clock, for synchronisation

MASTER AND SLAVE MODE OPERATION

The digital audio interface can be configured as a Master or a Slave interface, using the MSTR

Figure 21 Master Mode

Figure 22 Slave Mode

In Master mode, LRCLK and BCLK are configured as outputs, and the WM8948 controls the timing

of the data transfer on the ADCDAT and DACDAT pins.

In Master mode, the LRCLK frequency is determined automatically according to the sample rate (see

“Clocking and Sample Rates”). The BCLK frequency is set by the BCLK_DIV register. BCLK_DIV

must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the

complete data words from the ADCs and to the DACs.

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