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WM8948ECS/R Datenblatt(PDF) 82 Page - Wolfson Microelectronics plc |
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WM8948ECS/R Datenblatt(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 189 page ![]() WM8948 Production Data w PD, May 2011, Rev 4.1 82 In order to follow the above requirements for FVCO, the value of FLL_OUTDIV should be selected according to the desired output FOUT, as described in Table 52. OUTPUT FREQUENCY FOUT FLL_OUTDIV 2.8125 MHz - 3.125 MHz 4h (divide by 32) 5.625 MHz - 6.25 MHz 3h (divide by 16) 11.25 MHz - 12.5 MHz 2h (divide by 8) 22.5 MHz - 25 MHz 1h (divide by 4) 45 MHz - 50 MHz 0h (divide by 2) Table 52 Selection of FLL_OUTDIV The value of FLL_FRATIO should be selected as described in Table 53. REFERENCE FREQUENCY FREF FLL_FRATIO 1MHz - 13.5MHz 0h (divide by 1) 256kHz - 1MHz 1h (divide by 2) 128kHz - 256kHz 2h (divide by 4) 16kHz - 128kHz 3h (divide by 8) Less than 16kHz 4h (divide by 16) Table 53 Selection of FLL_FRATIO In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLL_OUTDIV) The value of FLL_N and FLL_K can then be determined as follows: N.K = FVCO / (FLL_FRATIO x FREF) Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable. In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field. This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an integer value, as illustrated in the following example: If N.K = 8.192, then K = 0.192. Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex). For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a non- integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is within its recommended limits of 90-100 MHz. The register fields that control the FLL are described in Table 54. Example settings for a variety of reference frequencies and output frequencies are shown in Table 55. |
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