WM8948ECSSLASHR datasheet(25/189 Pages) WOLFSON

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Production Data

WM8948

PD, May 2011, Rev 4.1

INPUT PGA ENABLE

The input PGAs (Programmable Gain Amplifiers) are enabled using register bits INPPGAR_ENA and

INPPGAL_ENA, as described in Table 1.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management 1

INPPGAR_ENA

Right Input PGA Enable

0 = Disabled

1 = Enabled

INPPGAL_ENA

Left Input PGA Enable

0 = Disabled

1 = Enabled

Table 1 Input PGA Enable

To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled.

See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and

BIAS_ENA.

INPUT PGA CONFIGURATION

Microphone and Line level audio inputs can be connected to the WM8948 in single-ended or

differential configurations. (These two configurations are illustrated in Figure 62 and Figure 63 in the

section describing the external components requirements - see “Applications Information”.)

For single-ended microphone inputs, the microphone signal is connected to the non-inverting input of

the PGAs, whilst the inverting inputs of the PGAs are connected to VMID. For differential microphone

inputs, the non-inverted microphone signal is connected to the non-inverting input of the PGAs, whilst

the inverted (or ‘noisy ground’) signal is connected to the inverting input pins.

Line level inputs are connected in the same way as a single-ended microphone signal.

The non-inverting input of the PGAs is configured using the P_PGAR_SEL and P_PGAL_SEL

registers. These registers allow the selection of three possible input pins to the associated PGA.

When the AUX1 or AUX2 pin is used as an audio input, that pin must be configured for audio using

the AUX1_AUDIO or AUX2_AUDIO register bits.

The inverting input of the PGAs is configured using MICRN_TO_N_PGAR and MICLN_TO_N_PGAL.

These registers allow the PGA to operate in either single-ended or pseudo-differential configuration.

The registers for configuring the Input PGAs are described in Table 2.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R39 (27h)

Input Ctrl

AUX2_AUDIO

AUX2 pin configuration

0 = Non-Audio signal

1 = AC-coupled Audio signal

AUX1_AUDIO

AUX1 pin configuration

0 = Non-Audio signal

1 = AC-coupled Audio signal

MICRN_TO_N_

PGAR

Right Input PGA Inverting Input

Select

0 = Connected to VMID

1 = Connected to IN2R

MICLN_TO_N_

PGAL

Left Input PGA Inverting Input

Select

0 = Connected to VMID

1 = Connected to IN2L

WM8948ECS/R Datenblatt(PDF) 25 Page - Wolfson Microelectronics plc

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