WM8948ECSSLASHR datasheet(78/189 Pages) WOLFSON

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WM8948

Production Data

PD, May 2011, Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

interface

15:14

DACDATA_

PULL [1:0]

DACDAT pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

13:12

FRAME_PULL

[1:0]

LRCLK pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

11:10

BCLK_PULL

[1:0]

BCLK pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

Table 49 Pull-Up and Pull-Down Control

CLOCKING AND SAMPLE RATES

The internal clocks for the CODEC and Digital Audio Interface are derived from a common internal

clock source, SYSCLK. This clock can either be derived directly from MCLK, or may be generated

using the Frequency Locked Loop (FLL) using MCLK as a reference. All commonly-used audio

sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional

flexibility for a wider range of MCLK frequencies.

The WM8948 supports a wide range of standard audio sample rates from 8kHz to 48kHz. When the

ADC and DAC are both enabled, they operate at the same sample rate, fs.

Other functions such as the AUXADC, Touch Panel controller, Interrupts, GPIO input de-bounce and

PGA zero-cross timeouts are clocked using a free-running oscillator.

The control registers associated with Clocking and Sample Rates are described in Table 50.

The overall clocking scheme for the WM8948 is illustrated in Figure 32.

Figure 32 WM8948 Clocking Overview

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