Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

Preview PDF HTML

WM8948ECS/R Datenblatt(PDF) 21 Page - Wolfson Microelectronics plc

Teilenummer WM8948ECS/R
Bauteilbeschribung  Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller
PDF  189 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8948ECS/R Datenblatt(HTML) 21 Page - Wolfson Microelectronics plc

Back Button WM8948ECS/R Datasheet HTML 17Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 18Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 19Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 20Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 21Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 22Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 23Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 24Page - Wolfson Microelectronics plc WM8948ECS/R Datasheet HTML 25Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 189 page
background image
Production Data
WM8948
w
PD, May 2011, Rev 4.1
21
CS
(input)
SCLK
(input)
SDA
(input)
tCSU
tCHO
tSCH
tSCL
tSCY
tDHO
tDSU
Figure 6 Control Interface Timing - 3-wire (SPI) Control Mode (Write Cycle)
Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device
SCLK
(input)
SDA
(output)
tDL
CS
(input)
Figure 7 Control Interface Timing - 3-wire (SPI) Control Mode (Read Cycle)
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25
oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CS
¯ ¯ falling edge to SCLK rising edge
tCSU
40
ns
SCLK falling edge to CS
¯ ¯ rising edge
tCHO
10
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDA to SCLK set-up time
tDSU
40
ns
SDA to SCLK hold time
tDHO
10
ns
Pulse width of spikes that will be suppressed
tps
0
5
ns
SCLK falling edge to SDA output transition
tDL
40
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com