WM8948ECSSLASHR datasheet(81/189 Pages) WOLFSON

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Production Data

WM8948

PD, May 2011, Rev 4.1

FREQUENCY LOCKED LOOP (FLL)

The integrated FLL can be used to generate SYSCLK from a wide variety of different reference

sources and frequencies. The FLL uses MCLK as its reference, which may be a high frequency (eg.

12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is tolerant of jitter and may be

used to generate a stable SYSCLK from a less stable input signal. The FLL characteristics are

summarised in “Electrical Characteristics”.

The FLL is enabled using the FLL_ENA register bit. At initial power on the VMID voltage must be

allowed to settle at its final vale before enabling the FLL. Note that, when changing FLL settings, it is

recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other

recommended that the FLL be reset by setting FLL_ENA to 0.

The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK) by 1, 2, 4 or

8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it

is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected.

The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only

the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should

be set to the recommended value.

The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real

number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the

fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the

field FLL_FRAC.

Power consumption in the FLL is reduced in integer mode; however, the performance may also be

reduced, with increased noise or jitter on the output.

If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie.

FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.

For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode

must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to

produce a non-integer value of N.K.

The FLL output frequency is generated according to the following equation:

FOUT = (FVCO / FLL_OUTDIV)

The FLL operating frequency, FVCO is set according to the following equation:

FVCO = (FREF x N.K x FLL_FRATIO)

FREF is the input frequency, as determined by FLL_CLK_REF_DIV.

FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.

Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed

across the full range of device operating temperatures.

WM8948ECS/R Datenblatt(PDF) 81 Page - Wolfson Microelectronics plc