WM8948ECSSLASHR datasheet(80/189 Pages) WOLFSON

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WM8948

Production Data

PD, May 2011, Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:5

SYSCLK_DIV

[2:0]

000

SYSCLK Clock divider

(Sets the scaling for either the

MCLK or FLL clock output,

depending on SYSCLK_SRC)

000 = divide by 1

001 = divide by 1.5

010 = divide by 2

011 = divide by 3

100 = divide by 4

101 = divide by 6

110 = divide by 8

111 = divide by 12

TOCLK_ENA

TOCLK Enabled

(Enables timeout clock for GPIO

level detection, AMU, and PGA zero

cross timeout)

0 = Disabled

1 = Enabled

R7 (07h)

Additional

control

3:0

SR [3:0]

1101

Audio Sample Rate select

0011 = 8kHz

0100 = 11.025kHz

0101 = 12kHz

0111 = 16kHz

1000 = 22.05kHz

1001 = 24kHz

1011 = 32kHz

1100 = 44.1kHz

1101 = 48kHz

Table 50 Clocking and Sample Rate Control

DIGITAL MIC CLOCKING

When any GPIO is configured as DMICCLK output, the WM8948 outputs a clock which supports

Digital Mic operation at the ADC sampling rate. Although the ADC is not used, the SYSCLK and

Sample Rate control fields must still be set as they would for ADC operation.

The clock frequencies for each of the sample rates is shown in Table 51

PCM SAMPLE RATE

DMICCLK

FS RATE

8kHz

1.024MHz

128fs

11.025kHz

1.411MHz

128fs

12kHz

1.536MHz

128fs

16kHz

2.048MHz

128fs

22.05kHz

2.8224MHz

128fs

24kHz

3.072MHz

128fs

32kHz

2.048MHz

64fs

44.1kHz

2.8224MHz

64fs

48kHz

3.072MHz

64fs

Table 51 Digital Microphone Clock Frequencies

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