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WM8948ECS/R Datenblatt(PDF) 144 Page - Wolfson Microelectronics plc

Teilenummer WM8948ECS/R
Bauteilbeschribung  Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller
PDF  189 Pages
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Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8948ECS/R Datenblatt(HTML) 144 Page - Wolfson Microelectronics plc

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WM8948
Production Data
w
PD, May 2011, Rev 4.1
144
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R38 (26h)
Video Buffer
7
VB_ENA
0
Video buffer enable
0 = Disabled
1 = Enabled
6
VB_QBOOST
0
Video buffer filter Q-Boost control
0 = Disabled
1 = Enabled
5
VB_GAIN
0
Video buffer gain
0 = 0dB (=6dB unloaded)
1 = 6dB (=12dB unloaded)
4:2
VB_DISOFF
[2:0]
111
Video buffer DC offset control
000 = Reserved
001 = 40mV offset
010 = Reserved
011 = 20mV offset
100 = Reserved
101 = Reserved
110 = Reserved
111 = 0mV offset
Note – the specified offset applies to the 0dB gain
setting (VB_GAIN=0). When 6dB gain is selected, the
DC offset is doubled.
1
VB_PD
0
Video buffer pull-down
0 = pull-down disabled
1 = pull-down enabled
0
VB_CLAMP
0
Enable the clamp between the video input and ground
0 = no clamp
1 = Video buffer input is clamped to ground
Register 26h Video Buffer
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R39 (27h)
Input ctrl
8
AUX2_AUDIO
0
AUX2 pin configuration
0 = Non-Audio signal
1 = AC-coupled Audio signal
7
AUX1_AUDIO
0
AUX1 pin configuration
0 = Non-Audio signal
1 = AC-coupled Audio signal
6
MICB_LVL
0
Microphone Bias Voltage control
0 = 0.9 x LDOVOUT
1 = 0.65 x LDOVOUT
5
MICRN_TO_N
_PGAR
1
Right Input PGA Inverting Input Select
0 = Connected to VMID
1 = Connected to IN2R
4
MICLN_TO_N_
PGAL
1
Left Input PGA Inverting Input Select
0 = Connected to VMID
1 = Connected to IN2L
3:2
P_PGAR_SEL
[1:0]
01
Right Input PGA Non-Inverting Input Select
00 = Connected to IN2R
01 = Connected to IN1R
10 = Connected to AUX2
11 = Reserved



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