SPRUG18 datasheet(127/214 Pages) TI

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TMS320C6474

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SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.8.3.8

PLLDIV Divider Ratio Change Status Register

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the

PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only

change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be

automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in

Figure 7-18 and described in Table 7-32.

Reserved

R-0

Reserved

SYS13

Rsvd

SYS11

Reserved

R-0

R/W-0

R-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-18. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]

Table 7-32. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit

Field

Value

Description

31:13

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYS13

Identifies when the SYSCLK13 divide ratio has been modified.

SYSCLK13 ratio has not been modified. When GOSET is set, SYSCLK13 will not be affected.

SYSCLK13 ratio has been modified. When GOSET is set, SYSCLK13 will change to the new ratio.

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYS11

Identifies when the SYSCLK11 divide ratio has been modified.

SYSCLK11 ratio has not been modified. When GOSET is set, SYSCLK11 will not be affected.

SYSCLK11 ratio has been modified. When GOSET is set, SYSCLK11 will change to the new ratio.

2:0

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Peripheral Information and Electrical Specifications

127

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