SPRUG18 datasheet(126/214 Pages) TI

126 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.8.3.7

PLL Controller Clock Align Control Register

The PLL controller clock align control register (ALNCTL) is shown in Figure 7-17 and described in

Table 7-31.

Reserved

R-0

Reserved

Rsvd

ALN13

Rsvd

ALN11

Reserved

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-17. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]

Table 7-31. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit

Field

Value

Description

31:14

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Reserved

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

ALN13

SYSCLK13 alignment. Do not change the default values of these fields.

Do not align SYSCLK13 to other SYSCLKs during GO operation. If SYS13 in DCHANGE is set to

1, SYSCLK13 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

Align SYSCLK13 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.

The SYSCLK13 ratio is set to the ratio programmed in the RATIO bit in PLLDIV13.

Reserved

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

ALN11

SYSCLK11 alignment. Do not change the default values of these fields.

Do not align SYSCLK11 to other SYSCLKs during GO operation. If SYS11 in DCHANGE is set to

1, SYSCLK11 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

Align SYSCLK11 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.

The SYSCLK11 ratio is set to the ratio programmed in the RATIO bit in PLLDIV11.

9:0

Reserved

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

126

Peripheral Information and Electrical Specifications

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