SPRUG18 datasheet(130/214 Pages) TI

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DDR.PLL

DD218

DDR.PLLController

PLLOUT

x10

DDR2

PHY

÷ 2

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.9

PLL2 and PLL2 Controller

The secondary PLL controller generates interface clocks for the DDR2 memory controller. The CLKIN2

input for PLL2 is DDRREFCLK. It is a differential clock input and is applied at the DDRREFCLKP and

DDRREFCLKN pins. When coming out of power-on reset, PLL2 is enabled and initialized.

As shown in Figure 7-21, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is

fixed to a x10 multiplier rate.

PLL2 power is supplied externally via the PLL2 power supply (AVDD218). An external PLL filter circuit must

be added to AVDD218 as shown in Figure 7-21. The 1.8-V supply for the EMI filter must be from the same

1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter manufacturer Murata.

For more information on the external PLL filter or the EMI filter, see the TMS320C6474 Hardware Design

Guide application report (literature number SPRAAW7).

All PLL external components (capacitors and the EMI filter) should be placed as close to the C64x+ DSP

device as possible. For the best performance, TI requires that all the PLL external components be on a

single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(capacitors and the EMI filter). The minimum CLKIN2 rise and fall times should also be observed.

Figure 7-21. PLL2 Block Diagram

7.9.1

PLL2 Controller Device-Specific Information

7.9.1.1

Internal Clocks and Maximum Operating Frequencies

As shown in Figure 7-21, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2

memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT0[P/N]

and DDR2CLKOUT1[P/N]. Note that, internally, the data bus interface of the DDR2 memory controller is

clocked by SYSCLK2 and PLL1 controller.

Note that there is a minimum and maximum operating frequency for DDRREFCLK and PLLOUT. The

clock generator and PLL multiplier must not be configured to exceed any of these constraints. For the PLL

clocks input and output frequency ranges, see Table 7-35. DDRREFCLK is a differential clock input to

PLL2 and is applied at the DDRREFCLKP and DDRREFCLKN pins.

Table 7-35. PLL2 Clock Frequency Ranges

MIN

MAX

UNIT

DDRREFCLK (PLLEN = 1)

66.7

MHz

PLLOUT

400

667

MHz

DDR2CLKOUT0[P/N] and DDR2CLKOUT1[P/N]

200

333

MHz

130

Peripheral Information and Electrical Specifications

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