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SPRUG18 Datenblatt(PDF) 129 Page - Texas Instruments

Teilenummer SPRUG18
Bauteilbeschribung  TMS320C6474 Multicore Digital Signal Processor
PDF  214 Pages
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SPRUG18 Datenblatt(HTML) 129 Page - Texas Instruments

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CLKIN
TMS320C6474
www.ti.com
SPRS552H
– OCTOBER 2008 – REVISED APRIL 2011
7.8.4
PLL1 Controller Input and Output Electrical Data/Timing
Table 7-34. Timing Requirements for SYSCLK and ALTCORECLK(1)
(see Figure 7-20)
NO.
PARAMETERS
MIN
MAX
UNIT
AIF Used, CORECLKSEL=0
1
tc(SYSCLK)
Cycle time, SYSCLK(N|P)
16.276
16.276
ns
2
tw(SYSCLKH)
Pulse duration, SYSCLK(N|P) high
0.4C
ns
3
tw(SYSCLKL)
Pulse duration, SYSCLK(N|P) low
0.4C
ns
4
tt(SYSCLK)
Transition time, SYSCLK(N|P)
50
1300
ps
5
tj(SYSCLK)
Period Jitter (RMS), SYSCLK(N|P)
4
ps
AIF Used, CORECLKSEL=1
1
tc(SYSCLK)
Cycle time, SYSCLK(N|P)
6.51
16.276
ns
2
tw(SYSCLKH)
Pulse duration, SYSCLK(N|P) high
0.4C
ns
3
tw(SYSCLKL)
Pulse duration, SYSCLK(N|P) low
0.4C
ns
4
tt(SYSCLK)
Transition time, SYSCLK(N|P)
50
1300
ps
5
tj(SYSCLK)
Period Jitter (RMS), SYSCLK(N|P)
4
ps
CORECLKSEL=1
1
tc(ALTCORECLK)
Cycle time, ALTCORECLK(N|P)
16(2)
25.00
ns
2
tw(ALTCORECLK)
Pulse duration, ALTCORECLK(N|P) high
0.4C
ns
3
tw(ALTCORECLKL)
Pulse duration, ALTCORECLK(N|P) low
0.4C
ns
4
tt(ALTCORECLK)
Transition time, ALTCORECLK(N|P)
50
1300
ps
5
tj(ALTCORECLK)
Period Jitter (peak-to-peak), ALTCORECLK(N|P)
100
ps
SYSCLKOUT
1
tc(CKO)
Cycle time, SYSCLKOUT
10C
32C
ns
2
tw(CKOH)
Pulse duration, SYSCLKOUT high
4C - 0.7
32C + 0.7
ns
3
tw(CKOL)
Pulse duration, SYSCLKOUT low
4C - 0.7
32C + 0.7
ns
4
tt(CKO)
Transition time, SYSCLKOUT
1
ns
(1)
If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency, in ns.
(2)
For the 850-MHz device, the minimum ALTCORECLK(N|P) must initially be 18.83 ns due to the boot ROM setting the default PLL1
multiplier to x16, resulting in SYSCLKOUT = 850 MHz.
Figure 7-20. CLKIN Timing
Copyright
© 2008–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
129
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