SPRUG18 datasheet(131/214 Pages) TI

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DDRREFCLK(N|P)

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.9.1.2

PLL2 Controller Operating Modes

Unlike the PLL1 controller which can operate in by_pass and _PLL mode, the PLL2 controller only

operates in PLL mode. In this mode, SYSREFCLK is generated outside the PLL2 controller by dividing the

output by two.

The PLL2 controller is affected by power-on reset and warm reset. During these resets, the PLL2

controller registers get reset to their default values. The internal clocks of the PLL2 controller are also

affected as described in Section 7.7, Reset Controller.

PLL2 is only unlocked during the power-up sequence (see Section 7.7, Reset Controller) and is locked by

the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

7.9.2

PLL2 Controller Input and Output Electrical Data/Timing

Table 7-36. Timing Requirements for DDRREFCLK(N|P)(1)

(see Figure 7-22)

NO.

PARAMETERS

MIN

MAX

UNIT

tc(DDRREFCLK)

Cycle time, DDRREFCLK(N|P)

tw(DDRREFCLKH)

Pulse duration, DDRREFCLK(N|P) high

0.4C

tw(DDRREFCLKL)

Pulse duration, DDRREFCLK(N|P) low

0.4C

tt(DDRREFCLK)

Transition time, DDRREFCLK(N|P)

1300

tj(DDRREFCLK)

Period jitter (peak-to-peak), DDRREFCLK(N|P)

0.02 x

tc(DDRREFCLK)

(1)

C=1/DDRREFCLK(N|P)

Figure 7-22. DDRREFCLK(N|P) Timing

Peripheral Information and Electrical Specifications

131

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