SPRUG18 datasheet(133/214 Pages) TI

133 / 214 page

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.10.2 DDR2 Memory Controller Peripheral Register Description(s)

The memory map of the DDR2 controller is shown in Table 7-37.

Table 7-37. DDR2 Memory Controller Registers

HEX ADDRESS

ACRONYM

7000 0000

MIDR

DDR2 Memory Controller Module and Revision Register

7000 0004

DMCSTAT

DDR2 Memory Controller Status Register

7000 0008

SDCFG

DDR2 Memory Controller SDRAM Configuration Register

7000 000C

SDRFC

DDR2 Memory Controller SDRAM Refresh Control Register

7000 0010

SDTIM1

DDR2 Memory Controller SDRAM Timing 1 Register

7000 0014

SDTIM2

DDR2 Memory Controller SDRAM Timing 2 Register

7000 0018

Reserved

7000 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

7000 0024 - 7000 004C

Reserved

7000 0050 - 7000 0078

Reserved

7000 007C - 7000 00BC

Reserved

7000 00C0 - 7000 00E0

Reserved

7000 00E4

DMCCTL

DDR2 Memory Controller Control Register

7000 00E8 - 7000 00EC

Reserved

7000 00F0

DDR2IO

Control Register

DDR2 ODT control register is at 0x7000 00F0

Bits 1:0 are the ODT status, these bits are Read/Write

00 no termination

01 half termination

11 full termination

Bits 31:2 are Reserved

7000 00F4 - 7000 00FC

Reserved

7000 0100 - 7FFF FFFF

Reserved

Peripheral Information and Electrical Specifications

133

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