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SPRUG18 Datenblatt(PDF) 134 Page - Texas Instruments

Teilenummer SPRUG18
Bauteilbeschribung  TMS320C6474 Multicore Digital Signal Processor
PDF  214 Pages
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Hersteller  TI [Texas Instruments]
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SPRUG18 Datenblatt(HTML) 134 Page - Texas Instruments

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DDRREFCLK(N|P)
5
TMS320C6474
SPRS552H
– OCTOBER 2008 – REVISED APRIL 2011
www.ti.com
7.10.3 DDR2 Memory Controller Electrical Data/Timing
The TMS320C6474 DDR2 Implementation Guidelines application report (literature number SPRAAW8)
specifies a complete DDR2 interface solution for the C6474 device as well as a list of compatible DDR2
devices. TI has performed the simulation and system characterization to ensure all DDR2 interface timings
in this solution are met.
TI only supports designs that follow the board design guidelines outlined in the SPRAAW8
application report.
Table 7-38. Timing Requirements for DDRREFCLK(N|P)(1)
(see Figure 7-23)
NO.
PARAMETERS
MIN
MAX
UNIT
1
tc(DDRREFCLK)
Cycle time, DDRREFCLK(N|P)
15
25
ns
2
tw(DDRREFCLKH)
Pulse duration, DDRREFCLK(N|P) high
0.4C
ns
3
tw(DDRREFCLKL)
Pulse duration, DDRREFCLK(N|P) low
0.4C
ns
4
tt(DDRREFCLK)
Transition time, DDRREFCLK(N|P)
50
1300
ps
5
tj(DDRREFCLK)
Period jitter (peak-to-peak), DDRREFCLK(N|P)
0.02 x
ps
tc(DDRREFCLK)
(1)
C=1/DDRREFCLK(N|P)
Figure 7-23. DDRREFCLK(N|P) Timing
134
Peripheral Information and Electrical Specifications
Copyright
© 2008–2011, Texas Instruments Incorporated
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Product Folder Link(s) :TMS320C6474



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